# US 12,604,721 B2 · Reverse embedded power structure for graphical processing unit chips and system-on-chip device packages

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- Number: US 12,604,721 B2
- Document ID: US12604721B2
- Status: Granted
- Kind: B2
- Application number: 17/964,583
- Filed: 2022-10-12
- Published: 2024-03-21
- Granted: 2026-04-14
- Earliest claimed: 2022-10-12
- Assignees: NVIDIA Corporation
- Applicants: NVIDIA Corporation
- Inventors: Shawn Xiao; Justin Jiang; Henry Li; Jerry Zhou; Joey Jiao
- Web page: https://patentgrep.com/patent/US12604721B2

## CPC

- H10W 20/427: {Power or ground buses}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/019: {of bond pads}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/50: Bond wires
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H10W 74/01: Manufacture or treatment
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10W 90/00: Package configurations
- H10W 44/00: Electrical arrangements for controlling or matching impedance
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5366: {the bond wires having kinks}
- H10W 72/879: {Bump connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A die including a die body having a first body surface, a second body surface on an opposite side of the die body as the first body surface, an interconnect region adjacent to the first body surface including interconnect dielectric layers with metal lines and vias, a transistor region above the interconnect region, the metal lines and vias making electrical connections to one or more power rails of the transistor region and electrically connected to transistors of the transistor region, a power region above the transistor region including an electro-conductive film on the second body surface and TSVs in the power region, an outer end of the TSV contacting the film and an embedded end of the TSVs contacting one of the power rails. A method of manufacturing an IC package and computer with the IC package are also disclosed.

## Claims

### Claim 1

A die, comprising:
a die body, the die body having a first body surface, a second body surface on an opposite side of the die body as the first body surface, the die body including:
an interconnect region located adjacent to the first body surface, the interconnect region including interconnect dielectric layers with metal lines and vias;
a transistor region located above the interconnect region, wherein the metal lines and vias make electrical connections to one or more power rails of the transistor region and the power rails are electrically connected to one or more transistors of the transistor region; and
a power region located above the transistor region, wherein the power region includes embedded TSVs and an electro-conductive film on the second body surface that traverses the second body surface to a side edge of the die body and contacts one or more solder bumps on the side edge of the die body, wherein for each one of the TSVs, an outer end of the TSV contacts the electro-conductive film and an embedded end of the TSVs contacts one of the power rails of the transistor region.

### Claim 2 (depends on 1)

The die of claim 1, wherein a hole of the TSV contains a metal plug.

### Claim 3 (depends on 1)

The die of claim 1, wherein a diameter of the hole is a value in a range from 0.001 to 1000 microns.

### Claim 4 (depends on 1)

The die of claim 1, wherein a thickness of the electro-conductive film is a value in a range from 1 to 1000 microns.

### Claim 5 (depends on 1)

The die of claim 1, further including a die substrate wherein the die body is located on a first substrate surface of the die substrate, one or more substrate conductive lines are located on the first substrate surface and a wire bond electrically connects the substrate conductive lines to the electro-conductive films.

### Claim 6 (depends on 5)

The die of claim 5, wherein one end of the wire bond contacts a first solder bump located on a side edge of the die body, the first solder bump contacting the electro-conductive films and an opposite end of the wire bond contacts a die substrate solder bump on the first substrate surface, the die substrate solder bump contacting one of the substrate conductive lines.

### Claim 7 (depends on 5)

The die of claim 5, wherein the die and the die substrate are part of an IC package, wherein the die substrate is mounted to a package substrate, the package substrate including package conductive lines and the package conductive lines electrically connected to form a first electric current pathway to the transistors of the die body, the first pathway including: the substrate conductive lines, the wire bond, the die substrate solder bump, the electro-conductive films and the TSVs of the power region of the die body.

### Claim 8 (depends on 7)

The die of claim 7, wherein the package conductive lines are electrically connected to form a second electric current pathway to the transistors of the die body, the second pathway including: die substrate solder balls, die substrate vias and die substrate mounting pads of the die substrate, and, the metal lines and vias of the power region interconnect region of the die body.

### Claim 9 (depends on 7)

The die of claim 7, wherein the first electric current pathway and the second electric current pathway are independent conductive pathways through the die substrate to the transistor region of the die body.

### Claim 10

A method of manufacturing an IC package, comprising:
providing a die body, the die body having a first body surface, a second body surface on an opposite side of the die body as the first body surface and the die body including:
an interconnect region located adjacent to the first body surface, the interconnect region including interconnect dielectric layers with metal lines and vias;
a transistor region located above the interconnect region, wherein the metal lines and vias make electrical connections to one or more power rails of the transistor region and the power rails are electrically connected to one or more transistors of the transistor region; and
a power region located above the transistor region;
forming one or more TSVs through the power region including forming a hole through the power region, the hole stopping on one of the power rails of the transistor region and then filling the hole with a metal plug such that an embedded end of the TSVs contact one of the power rails of the transistor region;
forming an electro-conductive film on the second surface of the die body such that the electro-conductive film contacts an outer end of at least one of the TSVs; and
forming a solder bump on a side edge of the power region and in contact with the electro-conductive film.

### Claim 11 (depends on 10)

The method of claim 10, wherein the forming of the one or more TSVs includes the forming the hole by laser drilling or deep reaction ion etching processes and the filling the hole to form a metal plug by electroplating or physical vapor deposition.

### Claim 12 (depends on 10)

The method of claim 10, wherein a diameter of the etched hole is a value in a range from 0.001 to 1000 microns.

### Claim 13 (depends on 10)

The method of claim 10, wherein the forming of the electro-conductive film includes physical or chemical vapor deposition or electroplating of copper or tungsten to form the metal plug.

### Claim 14 (depends on 10)

The method of claim 10, wherein a thickness of the electro-conductive film is a value in a range from 1 to 1000 microns.

### Claim 15 (depends on 10)

The method of claim 10, further including depositing a sealing layer on the electro-conductive film.

### Claim 16 (depends on 15)

The method of claim 15, where the depositing of the sealing layer includes chemical vapor deposition of silicon oxide on the electro-conductive film.

### Claim 17 (depends on 10)

The method of claim 10, further including mounting the die body to a die substrate including connecting solder balls on the first surface of the die body to mounting pads located on a first substrate surface of the die substrate.

### Claim 18 (depends on 17)

The method of claim 17, further including forming a wire bond between the solder bump on a side edge of the power region and a die substrate solder bump on the first substrate surface, the die substrate solder bump contacting a substrate conductive line on the first substrate surface.

### Claim 19 (depends on 10)

A computer having one or more circuits that include the IC package of claim 10.

### Claim 20

A die, comprising:
a die body, the die body having a first body surface, a second body surface on an opposite side of the die body as the first body surface, the die body including:
an interconnect region located adjacent to the first body surface, the interconnect region including interconnect dielectric layers with metal lines and vias;
a transistor region located above the interconnect region, wherein the metal lines and vias make electrical connections to one or more power rails of the transistor region and the power rails are electrically connected to one or more transistors of the transistor region;
a power region located above the transistor region, wherein the power region includes an electro-conductive film on the second body surface, wherein for each one of the TSVs, an outer end of the TSV contacts the electro-conductive film and an embedded end of the TSVs contacts one of the power rails of the transistor region; and
a die substrate wherein the die body is located on a first substrate surface of the die substrate, one or more substrate conductive lines are located on the first substrate surface and a wire bond electrically connects the substrate conductive lines to the electro-conductive film.