# US 12,604,719 B2 · Semiconductor device having a through-via structure electrically connected to a contact structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,719 B2 - Document ID: US12604719B2 - Status: Granted - Kind: B2 - Application number: 18/075,535 - Filed: 2022-12-06 - Published: 2023-08-10 - Granted: 2026-04-14 - Earliest claimed: 2022-02-04 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Sohye Cho; Kwangjin Moon; Hojin Lee - Web page: https://patentgrep.com/patent/US12604719B2 ## CPC - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10D 30/0194: {the stacked channels having different properties} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/506: {having different thicknesses, sizes or shapes} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/121: {oriented parallel to substrates} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 84/0158: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10W 20/0245: {comprising use of blind vias during the manufacture} - H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 20/427: {Power or ground buses} - H10W 20/481: {on the rear surfaces of the wafers or substrates} - H10W 80/00: Direct bonding of chips, wafers or substrates - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 64/251: {Source or drain electrodes for field-effect devices} - H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10W 20/0698: {Local interconnections} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 90/00: Package configurations - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract A semiconductor device includes a first semiconductor substrate having a protruding active pattern, a gate structure, a source/drain region in the active pattern on a side of the gate structure, an interlayer insulating layer on the source/drain region, a contact structure connected to the source/drain region through the interlayer insulating layer, a through-via structure electrically connected to the contact structure and passing through the interlayer insulating layer and the first semiconductor substrate, a first bonding structure including a first insulating layer on the first semiconductor substrate and a first connection pad in the first insulating layer, a second bonding structure on the first bonding structure and including a second insulating layer bonded to the first insulating layer and a second connection pad in the second insulating layer and bonded to the first connection pad, and a second semiconductor substrate disposed on the second bonding structure. ## Claims ### Claim 1 A semiconductor device, comprising: a first semiconductor substrate having a first surface and a second surface opposite to each other; an active pattern protruding from the first surface of the first semiconductor substrate, the active pattern extending in a first direction; a gate structure in a region of the active pattern, the gate structure extending in a second direction intersecting the first direction; a source/drain region in the active pattern on a side of the gate structure; an interlayer insulating layer on the source/drain region; a contact structure extending through the interlayer insulating layer to connect to the source/drain region; a through-via structure electrically connected to the contact structure and passing through the interlayer insulating layer and the first semiconductor substrate; a first bonding structure including a first insulating layer on the second surface of the first semiconductor substrate and a first connection pad embedded in the first insulating layer, the first connection pad being connected to the through-via structure; a second bonding structure on the first bonding structure and including a second insulating layer bonded to the first insulating layer and a second connection pad embedded in the second insulating layer and bonded to the first connection pad; and a second semiconductor substrate on the second bonding structure. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, wherein the contact structure has an extension extending in the second direction and connected to the through-via structure. ### Claim 3 (depends on 1) The semiconductor device as claimed in claim 1, further comprising a first wiring portion on the interlayer insulating layer and electrically connected to each of the contact structure and the through-via structure. ### Claim 4 (depends on 3) The semiconductor device as claimed in claim 3, wherein the interlayer insulating layer has an upper surface coplanar with an upper surface of each of the contact structure and the through-via structure. ### Claim 5 (depends on 3) The semiconductor device as claimed in claim 3, further comprising a support substrate on the first wiring portion. ### Claim 6 (depends on 5) The semiconductor device as claimed in claim 5, wherein the support substrate includes a bonding insulating layer bonded to the first wiring portion. ### Claim 7 (depends on 1) The semiconductor device as claimed in claim 1, further comprising a second wiring portion between the second semiconductor substrate and the second bonding structure and electrically connected to the second connection pad. ### Claim 8 (depends on 7) The semiconductor device as claimed in claim 7, wherein the second wiring portion is configured to supply power to the source/drain region through the through-via structure. ### Claim 9 (depends on 8) The semiconductor device as claimed in claim 8, wherein the second semiconductor substrate includes a through-via passing through the second semiconductor substrate and connected to the second wiring portion. ### Claim 10 (depends on 1) The semiconductor device as claimed in claim 1, wherein the second semiconductor substrate includes a semiconductor substrate in which a logic or memory device is implemented. ### Claim 11 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first semiconductor substrate has a thickness of 1 μm or less. ### Claim 12 (depends on 1) The semiconductor device as claimed in claim 1, wherein the through-via structure includes a conductive material and an insulating barrier surrounding a side surface of the conductive material. ### Claim 13 (depends on 12) The semiconductor device as claimed in claim 12, wherein the through-via structure has a portion protruding from the second surface of the first semiconductor substrate, a bottom surface of the portion including the conductive material. ### Claim 14 (depends on 13) The semiconductor device as claimed in claim 13, wherein the first insulating layer includes: a first insulating film on the second surface of the first semiconductor substrate, the first insulating film having a surface coplanar with the bottom surface of the portion, and a second insulating film on the first insulating film, the second insulating film having a surface coplanar with a surface of the first connection pad. ### Claim 15 (depends on 1) The semiconductor device as claimed in claim 1, further comprising: channel layers on the active pattern, the channel layers being spaced apart from each other in a third direction, perpendicular to the first and second directions, and each of the channel layers extending in the first direction, wherein the gate structure includes a gate electrode surrounding the channel layers and extending in the second direction, and a gate insulating layer between the channel layers and the gate electrode and between the active pattern and the gate electrode. ### Claim 16 A semiconductor device, comprising: a device substrate structure including a first semiconductor substrate having a first surface and a second surface opposite to each other and an active pattern protruding from the first surface and extending in a first direction, an interlayer insulating layer on the active pattern, a through-via structure electrically connected to the active pattern and passing through the interlayer insulating layer and the first semiconductor substrate, and a first wiring portion on the interlayer insulating layer; a first bonding structure including a first insulating layer on the second surface of the first semiconductor substrate and a first connection pad embedded in the first insulating layer and connected to the through-via structure; a second bonding structure on the first bonding structure and including a second insulating layer bonded to the first insulating layer and a second connection pad embedded in the second insulating layer and bonded to the first connection pad; a power supply substrate structure including a second wiring portion on the second bonding structure and a second semiconductor substrate having a through-via connected to the second wiring portion; and a support substrate on the first wiring portion. ### Claim 17 (depends on 16) The semiconductor device as claimed in claim 16, wherein: the through-via structure has a width narrowing toward the second surface of the first semiconductor substrate, and the through-via has a width narrowing toward the second bonding structure. ### Claim 18 (depends on 16) The semiconductor device as claimed in claim 16, wherein a bonding interface of the first insulating layer and the second insulating layer includes a material different from a material in other portions of an interface between the first bonding structure and the second bonding structure. ### Claim 19 A semiconductor device, comprising: a first semiconductor substrate having a first surface and a second surface opposite to each other; an active pattern protruding from the first surface of the first semiconductor substrate, the active pattern extending lengthwise in a first direction; a gate structure in a region of the active pattern, the gate structure extending lengthwise in a second direction intersecting the first direction; a source/drain region on the active pattern on a side of the gate structure; an interlayer insulating layer on the source/drain region; a contact structure extending through the interlayer insulating layer to connect to the source/drain region; a through-via structure electrically connected to the contact structure; a first bonding structure including a first insulating layer on the second surface of the first semiconductor substrate and a first connection pad embedded in the first insulating layer, the first connection pad being connected to the through-via structure; a second bonding structure on the first bonding structure and including a second insulating layer bonded to the first insulating layer and a second connection pad embedded in the second insulating layer and bonded to the first connection pad; and a second semiconductor substrate on the second bonding structure, wherein the through-via structure extends from the first bonding structure through at least a portion of the interlayer insulating layer, and wherein an upper surface of the through-via structure is farther from the first surface of the first semiconductor substrate than an upper surface of the active pattern. ### Claim 20 (depends on 19) The semiconductor device as claimed in claim 19, wherein the upper surface of the through-via structure is farther from the first surface of the first semiconductor substrate than an upper surface of the source/drain region.