# US 12,604,718 B2 · Memory device and method of manufacturing the same

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- Number: US 12,604,718 B2
- Document ID: US12604718B2
- Status: Granted
- Kind: B2
- Application number: 17/882,370
- Filed: 2022-08-05
- Published: 2023-09-14
- Granted: 2026-04-14
- Earliest claimed: 2022-03-10
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Dae Hyun Kim; Sei Yon Kim
- Web page: https://patentgrep.com/patent/US12604718B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Provided herein may be a memory device and a method of manufacturing the same. The memory device may include a plurality of insulating layers and a plurality of gate lines configured to be alternately stacked, and a cell plug configured to pass through the plurality of insulating layers and the plurality of gate lines, wherein the plurality of gate lines, each made of a conductive material, are etched together with the plurality of insulating layers, and the cell plug includes a blocking layer, a charge trap layer, a tunnel insulating layer, a channel layer, and a core pillar.

## Claims

### Claim 1

A memory device, comprising:
a plurality of insulating layers and a plurality of gate lines configured to be alternately stacked; and
a cell plug configured to pass through the plurality of insulating layers and the plurality of gate lines,
wherein the plurality of gate lines includes a conductive material,
wherein the plurality of gate lines and the plurality of insulating layers have similar etch selectivity under the same etching gas,
wherein the cell plug comprises a blocking layer, a charge trap layer, a tunnel insulating layer, a channel layer, and a core pillar, and
wherein each of the plurality of gate lines is formed of a plurality of different conductive oxide layers.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein each of the plurality of insulating layers is formed of an oxide layer.

### Claim 3 (depends on 1)

The memory device according to claim 1, wherein a current flows through the plurality of different conductive oxide layers.

### Claim 4 (depends on 1)

The memory device according to claim 1, wherein the plurality of different conductive oxide layers are stacked between the plurality of insulating layers.

### Claim 5 (depends on 1)

The memory device according to claim 1, wherein at least one of the plurality of different conductive oxide layers is made of a material that is selected from among the following plurality of chemical formulas: AlxOy and LaxAlyOz, and
wherein each remaining conductive oxide layer, among the plurality of different conductive oxide layers, is made of at least one material that is selected from among the following plurality of chemical formulas: CrxOy, FexOy, InxSnyOz, InxOy, LaxMnyOz, RexOy, SrxTiyOz, SnxOy, TixOy, VxOy, and ZnxOy.

### Claim 6 (depends on 5)

The memory device according to claim 5,
wherein values of x, y, and z are numbers indicating a number of atoms of each element in each chemical formula, among the plurality of chemical formulas, and
wherein the values of x, y, and z in a chemical formula, among the plurality of chemical formulas, is equal to or different from the values of x, y, and z in another chemical formula, among the plurality of chemical formulas.