# US 12,604,717 B2 · Semiconductor structure and method of manufacturing the same

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- Number: US 12,604,717 B2
- Document ID: US12604717B2
- Status: Granted
- Kind: B2
- Application number: 18/310,539
- Filed: 2023-05-02
- Published: 2024-11-07
- Granted: 2026-04-14
- Earliest claimed: 2023-05-02
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Min-Chung Cheng
- Web page: https://patentgrep.com/patent/US12604717B2

## CPC

- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/076: {in via holes or trenches}
- H10W 20/43: Layouts of interconnections
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor structure is provided by embodiments of this disclosure, and the method includes the following steps. An insulating area and an active area are formed in a substrate. A first word line trench is formed in the active area. A first dielectric layer is deposited in the first word line trench and on the active area and the insulating area. A second word line trench is formed through etching the first dielectric layer. Besides, the second word line trench is linear and extends through the insulating area and the active area of the substrate, and a portion of the first dielectric layer is remained in a bottom of the second word line trench. Then, a word line structure is formed in the second word line trench. Moreover, a semiconductor structure is provided in this disclosure.

## Claims

### Claim 1

A semiconductor structure, comprising
a substrate, comprising an insulating area and an active area; and
a word line structure, linear and extending through the insulating area and the active area, the word line structure comprising:
a conductive layer; and
a dielectric layer, comprising a bottom portion contacting a bottom of the conductive layer and a side portion contacting a sidewall of the conductive layer, wherein the bottom portion of the dielectric layer is thicker than the side portion of the dielectric layer
wherein the bottom portion of the dielectric layer comprises a bottom dielectric layer and a bottom liner dielectric layer, and an interface is between the bottom dielectric layer and the bottom liner dielectric layer, and
wherein a width of the bottom liner dielectric layer vertically projected to the substrate is substantially identical to a width of the bottom dielectric layer vertically projected to the substrate.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1, wherein the word line structure further comprises:
a cap layer, disposed on the conductive layer.

### Claim 3 (depends on 1)

The semiconductor structure according to claim 1, wherein the active area comprises a plurality of source/drain regions, and the plurality of the source/drain regions are disposed on opposite sides of the conductive layer.

### Claim 4 (depends on 3)

The semiconductor structure according to claim 3, wherein a depth of the word line structure is a first depth, a depth of the bottom liner dielectric layer of the word line structure is a second depth, and a depth of each of the plurality of source/drain regions is a third depth.

### Claim 5 (depends on 4)

The semiconductor structure according to claim 4, wherein the first depth is greater than the second depth, and the second depth is greater than the third depth.