# US 12,604,709 B2 · Probe card configured to connect to a probe pad located in saw street of a semiconductor wafer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,604,709 B2
- Document ID: US12604709B2
- Status: Granted
- Kind: B2
- Application number: 18/105,029
- Filed: 2023-02-02
- Published: 2023-09-07
- Granted: 2026-04-14
- Earliest claimed: 2022-02-04
- Assignees: Skyworks Solutions, Inc.
- Applicants: Skyworks Solutions, Inc.
- Inventors: Guillaume Alexandre Blin; Engin Ibrahim Pehlivanoglu
- Web page: https://patentgrep.com/patent/US12604709B2

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- G01R 1/07342: {the body of the probe being at an angle other than perpendicular to test object, e.g. probe card}
- G01R 31/2601: {Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence)}
- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 90/00: Package configurations
- H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
- H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A probe card for testing or trimming or programming a semiconductor wafer including a first die including a first integrated circuit having a trimmable or programmable component. The probe card including at least one probe arranged to make electrical contact with at least one probe pad arranged on the wafer. The at least one probe pad being electrically connected to the trimmable or programmable component and being arranged in a saw street of the wafer.

## Claims

### Claim 1

A system comprising a semiconductor wafer and a probe card for testing or trimming or programming the semiconductor wafer, the semiconductor wafer including:
a first die including a first integrated circuit having a trimmable or programmable component, the trimmable or programmable component being configured to be trimmed or permanently altered in response to an electrical signal;
a saw street arranged adjacent to the first die;
a seal ring around the first die having a plurality of metal layers with vias between the plurality of metal layers;
a plurality of stacked conductors with vias between the plurality of stacked conductors, the plurality of stacked conductors passing through a gap in the seal ring to provide a conductive path through the seal ring; and
at least one probe pad electrically connected to the trimmable or programmable component, the at least one probe pad being arranged in the saw street and connected to the plurality of stacked conductors, the probe card including at least one probe arranged to make electrical contact with the at least one probe pad arranged in the saw street of the semiconductor wafer.

### Claim 2 (depends on 1)

The system of claim 1 wherein the semiconductor wafer further includes a second die, the first and second dies being separated by the saw street.

### Claim 3 (depends on 1)

The system of claim 1 wherein the at least one probe pad is electrically connected to the trimmable or programmable component by a conductor extending from the at least one probe pad to the trimmable or programmable component.

### Claim 4 (depends on 1)

The system of claim 1 wherein the trimmable or programmable component is a fuse or a one-time programmable device.

### Claim 5 (depends on 1)

The system of claim 1 wherein the trimmable or programmable component is a memory.

### Claim 6 (depends on 2)

The system of claim 2 wherein the first die further includes trimming control circuitry configured to control the trimming of the trimmable or programmable component, the trimmable or programmable component being connected to the at least one probe pad via the trimming control circuitry.

### Claim 7 (depends on 6)

The system of claim 6 wherein the trimming control circuitry is arranged in a saw street that separates the first and second dies.

### Claim 8 (depends on 7)

The system of claim 7 wherein the first integrated circuit further includes a plurality of trimmable or programmable components and the semiconductor wafer further includes a plurality of probe pads, each probe pad being electrically connected to a respective trimmable or programmable component.

### Claim 9 (depends on 8)

The system of claim 8 wherein the plurality of probe pads are located in the saw street.

### Claim 10 (depends on 1)

The system of claim 1 wherein the gap in the seal ring extends entirely through the seal ring.

### Claim 11 (depends on 1)

The system of claim 1 wherein the plurality of stacked conductors pass through a full height of the plurality of metal layers.

### Claim 12 (depends on 1)

The system of claim 1 wherein there are three stacked conductors with two vias.

### Claim 13 (depends on 1)

The system of claim 1 wherein the semiconductor wafer wherein the seal ring is arranged around the first integrated circuit between the first integrated circuit and a perimeter of the first die.

### Claim 14 (depends on 13)

The system of claim 13 wherein plurality of stacked conductors form part of a redistribution layer arranged over the seal ring.

### Claim 15 (depends on 1)

The system of claim 1 wherein the semiconductor wafer further includes:
a plurality of dies separated by at least one saw street, each die of the plurality of dies including an integrated circuit having at least one trimmable or programmable component;
a plurality of seal rings with each seal ring around one of the plurality of dies, and each seal ring having a plurality of metal layers with vias between the plurality of metal layers;
a plurality of stacked conductors with vias between the plurality of stacked conductors, the plurality of stacked conductors passing through a gap in each seal ring to provide a conductive path through each seal ring; and
a plurality of probe pads arranged in the at least one saw street and connected to the plurality of stacked conductors, at least one probe pad of the plurality of probe pads being electrically connected to the at least one trimmable or programmable component of more than one die.

### Claim 16 (depends on 15)

The system of claim 15 wherein the at least one probe pad of the plurality of probe pads is electrically connected to the at least one trimmable or programmable component of more than one die by a plurality of conductors.

### Claim 17 (depends on 15)

The system of claim 15 wherein at least a portion of a plurality of conductors extends along the at least one saw street to interconnect each die.

### Claim 18 (depends on 15)

The system of claim 15 wherein the plurality of dies are electrically connected by a plurality of conductors, the plurality of conductors extending through and between the plurality of dies, each conductor of the plurality of conductors being electrically connected to at least one trimmable or programmable component of the plurality of dies and at least one probe pad.

### Claim 19 (depends on 15)

The system of claim 15 wherein the at least one probe pad is electrically connected to the trimmable or programmable component by a conductor extending from the at least one probe pad to the trimmable or programmable component.

### Claim 20 (depends on 19)

The system of claim 19 wherein the conductor passes through a gap formed in an intermediate layer of a plurality of stacked metal layers, the intermediate layer being between a top and bottom layer of the plurality of stacked metal layers.