# US 12,604,689 B2 · Bracing structure, semiconductor device with the same, and method for fabricating the same

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- Number: US 12,604,689 B2
- Document ID: US12604689B2
- Status: Granted
- Kind: B2
- Application number: 18/413,414
- Filed: 2024-01-16
- Published: 2025-06-26
- Granted: 2026-04-14
- Earliest claimed: 2023-12-26
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Min-Chung Cheng
- Web page: https://patentgrep.com/patent/US12604689B2

## CPC

- H10P 50/283: {by chemical means}
- H10P 14/69394: {the material containing titanium, e.g. TiO2}
- H10W 74/10: characterised by their shape or disposition
- H10W 76/12: characterised by their shape
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a support bracing structure, a semiconductor device with the support bracing structure, and a method for fabricating the semiconductor device with the support bracing structure. The support bracing structure includes a first bracing layer including two connection portions respectively positioned on top surfaces of two adjacent bottom electrodes, and a frame portion bridging the two connection portions; and a protection layer including a first portion positioned on and conforming to an inner surface of the frame portion and positioned between the two connection portions. The inner surface of the frame portion is normal to the top surfaces of the two adjacent bottom electrodes.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
providing a substrate, forming a dielectric stack over the substrate with a top supporting layer atop, and forming a plurality of cell holes in the dielectric stack;
forming at least two adjacent bottom electrodes in the plurality of cell holes, wherein the at least two adjacent bottom electrodes respectively comprises a bottom portion oriented parallel to the substrate and a sidewall portion extending normally and upwardly from a border of the bottom portion;
forming an under layer over the top supporting layer, and forming an under-layer opening penetrating the under layer to partially expose the at least two adjacent bottom electrodes and the top supporting layer;
recessing the top supporting layer to form a recessed portion of the top supporting layer that partially exposes outer surfaces of the sidewall portions of the at least two adjacent bottom electrodes;
conformally forming a first portion of a protection layer on a sidewall of the recessed portion and a second portion of the protection layer on the outer surfaces of the sidewall portions; and
recessing the sidewall portions to form a first bracing layer and a second bracing layer, wherein the first bracing layer is formed on both the first portion and top surfaces of the sidewall portions, and the second bracing layer is formed on the second portion;
wherein the first bracing layer, the second bracing layer, and the protection layer together configure a support bracing structure.

### Claim 2 (depends on 1)

The method for fabricating the semiconductor device of claim 1, wherein the top surfaces of the sidewall portions are higher than a top surface of the recessed portion.

### Claim 3 (depends on 2)

The method for fabricating the semiconductor device of claim 2, wherein recessing the top supporting layer is achieved by performing an etching process using an etchant comprising sulfur hexafluoride, argon, and chlorine.

### Claim 4 (depends on 2)

The method for fabricating the semiconductor device of claim 2, wherein the protection layer comprises an oxide.

### Claim 5 (depends on 2)

The method for fabricating the semiconductor device of claim 2, wherein recessing the sidewall portions is achieved by performing an etching process using an etchant comprising argon, chlorine, and nitrogen.

### Claim 6 (depends on 2)

The method for fabricating the semiconductor device of claim 2, further comprising removing the recessed portion of the top supporting layer to form a side cave adjacent and underneath the first portion of the protection layer, and to expose a top dielectric layer of the dielectric stack.

### Claim 7 (depends on 6)

The method for fabricating the semiconductor device of claim 6, wherein removing the recessed portion of the top supporting layer is achieved by performing an etching process using an etchant comprising sulfur hexafluoride and argon.

### Claim 8 (depends on 6)

The method for fabricating the semiconductor device of claim 6, wherein the first bracing layer and the second bracing layer comprises titanium tetrafluoride or titanium oxide.

### Claim 9 (depends on 2)

The method for fabricating the semiconductor device of claim 2, further comprising removing the under layer after recessing the sidewall portions.

### Claim 10 (depends on 1)

The method for fabricating the semiconductor device of claim 1, wherein the top supporting layer comprises silicon nitride.