# US 12,604,686 B2 · Semiconductor chip and semiconductor package including the same

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- Number: US 12,604,686 B2
- Document ID: US12604686B2
- Status: Granted
- Kind: B2
- Application number: 18/135,927
- Filed: 2023-04-18
- Published: 2024-02-15
- Granted: 2026-04-14
- Earliest claimed: 2022-08-09
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yongho Kim; Jeonghoon Ahn
- Web page: https://patentgrep.com/patent/US12604686B2

## CPC

- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 72/019: {of bond pads}
- H10W 72/90: Bond pads, in general
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/792: {between multiple chips}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor chip and a semiconductor package, the semiconductor chip includes a semiconductor substrate; a through electrode penetrating the semiconductor substrate; a bonding pad including a first conductive pad connected to the through electrode, and a second conductive pad on a central portion of the first conductive pad, an outer portion of the first conductive pad protruding outwardly relative to a sidewall of the second conductive pad; and a pad insulating layer on the semiconductor substrate and surrounding a sidewall of the first conductive pad and the sidewall of the second conductive pad.

## Claims

### Claim 1

A semiconductor chip, comprising:
a semiconductor substrate;
a through electrode penetrating the semiconductor substrate;
a bonding pad including:
a first conductive pad connected to the through electrode, and
a second conductive pad on a central portion of the first conductive pad, an outer portion of the first conductive pad protruding outwardly relative to a sidewall of the second conductive pad; and
a pad insulating layer on the semiconductor substrate and surrounding a sidewall of the first conductive pad and the sidewall of the second conductive pad,
wherein the first conductive pad includes:
a first core metal layer; and
a first seed metal layer between a sidewall of the first core metal layer and the pad insulating layer and between a bottom surface of the first core metal layer and the through electrode.

### Claim 2 (depends on 1)

The semiconductor chip as claimed in claim 1,
wherein the outer portion of the first conductive pad has a ring shape continuously extending around the sidewall of the second conductive pad in a plan view.

### Claim 3 (depends on 1)

The semiconductor chip as claimed in claim 1,
wherein the second conductive pad includes:
a second core metal layer; and
a second seed metal layer between a sidewall of the second core metal layer and the pad insulating layer and between a bottom surface of the second core metal layer and the first conductive pad.

### Claim 4 (depends on 1)

The semiconductor chip as claimed in claim 1,
wherein the pad insulating layer includes:
a first insulating layer surrounding the sidewall of the first conductive pad; and
a second insulating layer on the first insulating layer and surrounding the sidewall of the second conductive pad.

### Claim 5 (depends on 4)

The semiconductor chip as claimed in claim 4,
wherein a material of the first insulating layer is different from a material of the second insulating layer.

### Claim 6 (depends on 5)

The semiconductor chip as claimed in claim 5, wherein:
the first insulating layer includes silicon nitride, and
the second insulating layer includes silicon oxide.

### Claim 7 (depends on 4)

The semiconductor chip as claimed in claim 4,
wherein a material of the first insulating layer is the same as a material of the second insulating layer.

### Claim 8 (depends on 1)

The semiconductor chip as claimed in claim 1,
wherein a length by which the outer portion of the first conductive pad protrudes laterally from the sidewall of the second conductive pad is about 1 μm to about 5 μm.

### Claim 9

A semiconductor package, comprising:
a first semiconductor substrate including a first surface and a second surface, which are opposite to each other;
a first through electrode penetrating the first semiconductor substrate;
a first bonding pad including:
a first conductive pad on the first surface of the first semiconductor substrate and connected to the first through electrode, and
a second conductive pad on a central portion of the first conductive pad, an outer portion of the first conductive pad protruding outwardly relative to a sidewall of the second conductive pad;
a first pad insulating layer on the first surface of the first semiconductor substrate and surrounding a sidewall of the first conductive pad and the sidewall of the second conductive pad;
a second semiconductor substrate on the first pad insulating layer;
a second through electrode penetrating the second semiconductor substrate;
a second bonding pad bonded to the first bonding pad and electrically connecting the second through electrode to the first bonding pad; and
a second pad insulating layer between the second semiconductor substrate and the first pad insulating layer and surrounding a sidewall of the second bonding pad,
wherein the second bonding pad includes:
a third conductive pad connected to the second through electrode; and
a fourth conductive pad between the third conductive pad and the second conductive pad and bonded to the second conductive pad,
wherein a central portion of the third conductive pad vertically overlaps the fourth conductive pad, and
wherein an outer portion of the third conductive pad protrudes outwardly relative to a sidewall of the fourth conductive pad.

### Claim 10 (depends on 9)

The semiconductor package as claimed in claim 9, wherein:
the outer portion of the first conductive pad has a ring shape continuously extending around the sidewall of the second conductive pad in a plan view, and
the outer portion of the third conductive pad has a ring shape continuously extending around the sidewall of the fourth conductive pad in a plan view.

### Claim 11 (depends on 9)

The semiconductor package as claimed in claim 9, wherein:
the first conductive pad includes:
a first core metal layer; and
a first seed metal layer between a sidewall of the first core metal layer and the first pad insulating layer and between a bottom surface of the first core metal layer and the first through electrode, and
the second conductive pad includes:
a second core metal layer; and
a second seed metal layer between a sidewall of the second core metal layer and the first pad insulating layer and between a bottom surface of the second core metal layer and the first conductive pad.

### Claim 12 (depends on 11)

The semiconductor package as claimed in claim 11, wherein:
the third conductive pad includes:
a third core metal layer; and
a third seed metal layer between a sidewall of the third core metal layer and the second pad insulating layer and between an upper surface of the third core metal layer and the second through electrode,
the fourth conductive pad includes:
a fourth core metal layer; and
a fourth seed metal layer between a sidewall of the fourth core metal layer and the second pad insulating layer and between an upper surface of the fourth core metal layer and the third conductive pad, and
an upper surface of the second core metal layer is in direct contact with a bottom surface of the fourth core metal layer.

### Claim 13 (depends on 9)

The semiconductor package as claimed in claim 9, wherein:
the first pad insulating layer includes:
a first insulating layer surrounding the sidewall of the first conductive pad; and
a second insulating layer on the first insulating layer and surrounding the sidewall of the second conductive pad, and
the second pad insulating layer includes:
a third insulating layer surrounding a sidewall of the third conductive pad; and
a fourth insulating layer between the second insulating layer and the third insulating layer and surrounding the sidewall of the fourth conductive pad.

### Claim 14 (depends on 13)

The semiconductor package as claimed in claim 13, wherein:
the first insulating layer and the third insulating layer each include silicon nitride, and
the second insulating layer and the fourth insulating layer each include silicon oxide.

### Claim 15 (depends on 13)

The semiconductor package as claimed in claim 13,
wherein the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer each include silicon oxide.

### Claim 16 (depends on 9)

The semiconductor package as claimed in claim 9,
wherein each of the first conductive pad and the second conductive pad has a rectangular shape in a cross-sectional view.

### Claim 17

A semiconductor package comprising a first semiconductor chip and a second semiconductor chip, which are bonded to each other, wherein:
the first semiconductor chip includes:
a first semiconductor substrate including a first surface and a second surface, which are opposite to each other;
a first through electrode penetrating the first semiconductor substrate;
a first bonding pad including a first conductive pad on the first surface of the first semiconductor substrate and connected to the first through electrode, and a second conductive pad on a central portion of the first conductive pad, an outer portion of the first conductive pad protruding outwardly relative to a sidewall of the second conductive pad; and
a first pad insulating layer on the first surface of the first semiconductor substrate and surrounding a sidewall of the first conductive pad and the sidewall of the second conductive pad,
the second semiconductor chip includes:
a second semiconductor substrate;
a second through electrode penetrating the second semiconductor substrate;
a second bonding pad bonded to the first bonding pad and including a third conductive pad connected to the second through electrode, and a fourth conductive pad between the third conductive pad and the second conductive pad, an outer portion of the third conductive pad protruding outwardly relative to a sidewall of the fourth conductive pad; and
a second pad insulating layer between the second semiconductor substrate and the first pad insulating layer and surrounding a sidewall of the second bonding pad,
the outer portion of the first conductive pad has a ring shape continuously extending around the sidewall of the second conductive pad in a plan view,
the outer portion of the third conductive pad has a ring shape continuously extending around the sidewall of the fourth conductive pad in a plan view,
a portion of the first pad insulating layer is between a bonding interface between the first semiconductor chip and the second semiconductor chip, and the outer portion of the first conductive pad,
a portion of the second pad insulating layer is between the bonding interface and the outer portion of the third conductive pad, and
each of the first conductive pad, the second conductive pad, the third conductive pad, and the fourth conductive pad has a rectangular shape in a cross-sectional view.

### Claim 18 (depends on 17)

The semiconductor package as claimed in claim 17, wherein:
the first conductive pad includes:
a first core metal layer; and
a first seed metal layer between a sidewall of the first core metal layer and the first pad insulating layer and between a bottom surface of the first core metal layer and the first through electrode,
the second conductive pad includes:
a second core metal layer; and
a second seed metal layer between a sidewall of the second core metal layer and the first pad insulating layer and between a bottom surface of the second core metal layer and the first conductive pad,
the third conductive pad includes:
a third core metal layer; and
a third seed metal layer between a sidewall of the third core metal layer and the second pad insulating layer and between an upper surface of the third core metal layer and the second through electrode,
the fourth conductive pad includes:
a fourth core metal layer; and
a fourth seed metal layer between a sidewall of the fourth core metal layer and the second pad insulating layer and between an upper surface of the fourth core metal layer and the third conductive pad, and
an upper surface of the second core metal layer is in direct contact with a bottom surface of the fourth core metal layer.