Memory cell, semiconductor device having the same, and methods of manufacturing the same

A semiconductor device, comprising:

• a first interconnect structure;
• a memory cell, disposed over the first interconnect structure, wherein the memory cell comprises:
• a heater, disposed over the first interconnect structure;
• a storage element layer, disposed over the heater;
• a first thermal insulating layer, interposed between the storage element layer and the heater, wherein a thermal conductivity of the first thermal insulating layer is less than a thermal conductivity of the storage element layer;
• a top electrode, disposed over the storage element layer;
• and
• an etching stop layer, extending along the top electrode, the first thermal insulating layer, the storage element layer and the heater;
• and
• a second interconnect structure, disposed over the memory cell, wherein in a cross-section of the semiconductor device along a stacking direction of the first interconnect structure and the second interconnect structure, the etching stop layer covers a sidewall of the heater and is between the first interconnect structure and the second interconnect structure.

A method of manufacturing a semiconductor device, comprising:

• providing a first interconnect structure;
• forming a memory cell over the first interconnect structure, comprising:
• forming a bottom electrode over the first interconnect structure;
• forming a first buffer material, a storage element material and a top electrode material over the bottom electrode;
• patterning the top electrode material, the storage element material and the first buffer material to form a top electrode, a storage element layer and a first buffer layer, wherein the storage element layer is disposed between the bottom electrode and the top electrode, the first buffer layer is interposed between the bottom electrode and the storage element layer, and a thermal conductivity of the first buffer layer is less than a thermal conductivity of the storage element layer, wherein the first buffer layer is in contact with a first surface of the bottom electrode;
• and
• disposing a protection layer covering the top electrode, the storage element layer and the first buffer layer, the bottom electrode being free of the protection layer, wherein a bottommost surface of the protection layer is substantially level with or above the first surface of the bottom electrode in a stacking direction of the bottom electrode and the first buffer layer;
• and
• forming a second interconnect structure over the memory cell.