# US 12,604,623 B2 · Display panel and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,623 B2 - Document ID: US12604623B2 - Status: Granted - Kind: B2 - Application number: 18/032,580 - Filed: 2022-06-08 - Published: 2024-11-14 - Granted: 2026-04-14 - Earliest claimed: 2022-06-08 - Assignees: Chengdu Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd.; BOE Technology Group Co., Ltd. - Inventors: Rong Wang; Fan He; Hongwei Ma; Xiangdan Dong; Cong Fan; Zhenhua Zhang - Web page: https://patentgrep.com/patent/US12604623B2 ## CPC - H10K 59/131: Interconnections, e.g. wiring lines or terminals - H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present disclosure provides a display panel and a display device. First interconnect lines of the display panel are connected to second data lines corresponding to first sub-pixels and third sub-pixels, and second interconnect sections of all the first interconnect lines are arranged in the same layer as a first source-drain metal layer or a second source-drain metal layer. ## Claims ### Claim 1 A display panel, comprising a display area and a peripheral area at least partially surrounding the display area, wherein along a first direction, the display area of the display panel comprises a first display area and second display areas on both sides of the first display area; wherein the display panel comprises: a base substrate; a driving circuit layer comprising a first source-drain metal layer and a second source-drain metal layer, wherein the first source-drain metal layer is arranged on a side of the base substrate, and the second source-drain metal layer is arranged on a side of the first source-drain metal layer away from the base substrate; a pixel layer comprising a plurality of pixel groups, wherein the pixel groups comprise first sub-pixels, second sub-pixels and third sub-pixels with different colors; a plurality of pads located in the peripheral area; a plurality of data lines respectively electrically connected to a plurality of the first sub-pixels, a plurality of the second sub-pixels and a plurality of the third sub-pixels, wherein the plurality of data lines are located in the display area and extend along a second direction, the plurality of data lines comprise a plurality of first data lines located in the first display area and a plurality of second data lines located in the second display areas, and the plurality of first data line are electrically connected to the plurality of pads; and a plurality of interconnect lines located in the display area and electrically connected to the plurality of second data lines and the plurality of pads, wherein the plurality of interconnect lines comprises a plurality of first interconnect lines and a plurality of second interconnect lines, the first interconnect lines are connected to second data lines corresponding to the first sub-pixels and the third sub-pixels, and the second interconnect lines are connected to second data lines corresponding to the second sub-pixels; wherein each of the plurality of interconnect lines comprises a first interconnect section extending along the first direction and a second interconnect section extending along a second direction and the first direction and the second direction intersect; wherein at least one second interconnect section is arranged between two adjacent first data lines, second interconnect sections of all the first interconnect lines are arranged in a same layer as the first source-drain metal layer or the second source-drain metal layer, and at least a part of second interconnect sections of the second interconnect lines are arranged in a same layer as the first source-drain layer or the second source-drain layer; wherein the driving circuit layer further comprises driving circuit islands distributed in an array, and each of the plurality of interconnect lines is arranged in a gap between the driving circuit islands. ### Claim 2 (depends on 1) The display panel according to claim 1, wherein the second interconnect sections of all the first interconnect lines are arranged in the same layer as the first source-drain metal layer, and the second interconnect sections of all the second interconnect lines are arranged in the same layer as the first source-drain metal layer. ### Claim 3 (depends on 1) The display panel according to claim 1, wherein the second interconnect sections of all the first interconnect lines are arranged in the same layer as the second source-drain metal layer, and the second interconnect sections of all the second interconnect lines are arranged in the same layer as the second source-drain metal layer. ### Claim 4 (depends on 1) The display panel according to claim 1, wherein the second interconnect sections of all the first interconnect lines are arranged in the same layer as the second source-drain metal layer, and the second interconnect sections of all the second interconnect lines are arranged in the same layer as the first source-drain metal layer. ### Claim 5 (depends on 1) The display panel according to claim 1, wherein the second interconnect sections of all the first interconnect lines are arranged in the same layer as the second source-drain metal layer, a part of second interconnect sections of the second interconnect lines are arranged in the same layer as the first source-drain metal layer, and another part of second interconnect sections of the second interconnect lines are arranged in the same layer as the second source-drain metal layer. ### Claim 6 (depends on 5) The display panel according to claim 5, wherein the second interconnect sections of the second interconnect lines are alternately distributed in the first source-drain metal layer and the second source-drain metal layer. ### Claim 7 (depends on 5) The display panel according to claim 5, wherein second interconnect sections of two second interconnect lines arranged symmetrically with respect to a central axis extending along the second direction are arranged in a same layer. ### Claim 8 (depends on 1) The display panel according to claim 1, wherein a plurality of adjacent first data lines are arranged as a plurality of first data line groups, a plurality of adjacent interconnect lines are arranged as a plurality of interconnect line groups, second interconnect sections of a plurality of adjacent interconnect lines form second interconnect section groups, and in at least part of the first display area, the first data line groups and the second interconnect section groups are alternately arranged one by one. ### Claim 9 (depends on 8) The display panel according to claim 8, wherein each of the second interconnect section groups comprises a second interconnect section of at least one first interconnect line and a second interconnect section of at least one second interconnect line, and the second interconnect section of the first interconnect line and the second interconnect section of the second interconnect line are arranged alternately. ### Claim 10 (depends on 8) The display panel according to claim 8, wherein each of the second interconnect section groups comprises a second interconnect section of at least one first interconnect line and second interconnect sections of at least two second interconnect lines, second interconnect section of all of the at least one first interconnect line is arranged in the same layer as the second source-drain metal layer, and a second interconnect section of at least one second interconnect line is arranged in the same layer as the first source-drain metal layer, a second interconnect section of at least one second interconnect line is arranged in the same layer as the second source-drain metal layer, the first sub-pixels are red sub-pixel pixels, the second sub-pixels are green sub-pixels, and the third sub-pixels are blue sub-pixels. ### Claim 11 (depends on 1) The display panel according to claim 1, wherein: the display area is arranged symmetrically with respect to a central axis extending along the second direction, in two adjacent second data lines, a second interconnect section corresponding to one of the two adjacent second data lines which is away from the central axis is arranged as farther away from the central axis as compared with a second interconnect section corresponding to the other one of the two adjacent second data lines which is close to the central axis. ### Claim 12 (depends on 1) The display panel according to claim 1, wherein the display area is arranged symmetrically with respect to a central axis extending along the second direction, in two adjacent second data lines, a first interconnect section corresponding to one of the two adjacent second data lines which is away from the central axis is arranged as closer to a corresponding pad as compared with a first interconnect section corresponding to the other one of the two adjacent second data lines which is close to the central axis. ### Claim 13 (depends on 1) The display panel according to claim 1, wherein the plurality of first data lines located in the first display area are arranged in the first source-drain metal layer or the second source-drain metal layer. ### Claim 14 (depends on 1) The display panel according to claim 1, wherein the driving circuit layer further comprises a transistor layer, the transistor layer is arranged between the base substrate and the first source-drain metal layer, the transistor layer is provided with driving circuits, and the driving circuits comprise thin film transistors, and the interconnect lines do not overlap with the thin film transistors. ### Claim 15 (depends on 14) The display panel according to claim 14, wherein any one of the driving circuit islands comprises one or more driving circuit areas corresponding to the driving circuits one to one, at least part of thin film transistors of a driving circuit are arranged in a corresponding driving circuit area. ### Claim 16 (depends on 15) The display panel according to claim 15, wherein: the second interconnect sections are arranged as a plurality of second interconnect section groups; in any one of the second interconnect section groups, the second interconnect sections are arranged adjacently in sequence and are located between two adjacent driving circuit island columns; and any two adjacent second interconnect section groups are isolated by a driving circuit island column. ### Claim 17 (depends on 1) The display panel according to claim 1, wherein: the transistor layer has a gate layer, the driving circuit layer further comprises an electrode initialization voltage line extending along the first direction, the electrode initialization voltage lines comprises a first initialization line and a second initialization line alternately connected, the first initialization line is arranged in the gate layer, and the second initialization line is arranged in the first source-drain metal layer, a part of the second interconnect sections are arranged in the first source-drain metal layer, and second interconnect sections located in the first source-drain metal layer overlap with the first initialization line. ### Claim 18 (depends on 17) The display panel according to claim 17, wherein all of the first interconnect sections are arranged in the same layer as the first source-drain metal layer or the gate layer, at least part of the second interconnect sections are arranged in the same layer as the second source-drain metal layer, the second interconnect sections located in the second source-drain metal layer are connected to corresponding first interconnect sections through interconnectors, and a portion of one of the first data lines adjacent to a corresponding interconnector is bent away from the interconnector to form an avoidance section, and the avoidance section overlaps a corresponding first interconnect section. ### Claim 19 A display device, comprising: a display panel; wherein the display panel comprises a display area and a peripheral area at least partially surrounding the display area, and along a first direction, the display area of the display panel comprises a first display area and second display areas on both sides of the first display area; wherein the display panel comprises: a base substrate; a driving circuit layer comprising a first source-drain metal layer and a second source-drain metal layer, wherein the first source-drain metal layer is arranged on a side of the base substrate, and the second source-drain metal layer is arranged on a side of the first source-drain metal layer away from the base substrate; a pixel layer comprising a plurality of pixel groups, wherein the pixel groups comprise first sub-pixels, second sub-pixels and third sub-pixels with different colors; a plurality of pads located in the peripheral area, a plurality of data lines respectively electrically connected to a plurality of the first sub-pixels, a plurality of the second sub-pixels and a plurality of the third sub-pixels, wherein the plurality of data lines are located in the display area and extend along a second direction, the plurality of data lines comprise a plurality of first data limes located in the first display area and a plurality of second data lines located in the second display areas, and the plurality of first data line are electrically connected to the plurality of pads; and a plurality of interconnect lines located in the display area and electrically connected to the plurality of second data lines and the plurality of pads, wherein the plurality of interconnect lines comprises a plurality of first interconnect lines and a plurality of second interconnect lines, the first interconnect lines are connected to second data lines corresponding to the first sub-pixels and the third sub-pixels, and the second interconnect lines are connected to second data lines corresponding to the second sub-pixels; wherein each of the plurality of interconnect lines comprises a first interconnect section extending along the first direction and a second interconnect section extending along a second direction and the first direction and the second direction intersect; wherein at least one second interconnect section is arranged between two adjacent first data lines, second interconnect sections of all the first interconnect lines are arranged in a same layer as the first source-drain metal layer or the second source-drain metal layer, and at least a part of second interconnect sections of the second interconnect lines are arranged in a same layer as the first source-drain layer or the second source-drain layer; wherein the driving circuit layer further comprises driving circuit islands distributed in an array, and each of the plurality of interconnect lines is arranged in a gap between the driving circuit islands.