# US 12,604,562 B2 · Semiconductor structure and manufacture method therefor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,562 B2 - Document ID: US12604562B2 - Status: Granted - Kind: B2 - Application number: 18/004,340 - Filed: 2020-09-24 - Published: 2023-09-07 - Granted: 2026-04-14 - Earliest claimed: 2020-09-24 - Assignees: Enkris Semiconductor, Inc. - Applicants: Enkris Semiconductor, Inc. - Inventors: Kai Cheng; Weihua Liu - Web page: https://patentgrep.com/patent/US12604562B2 ## CPC - H10H 20/812: within the light-emitting regions, e.g. having quantum confinement structures - H10H 20/813: having a plurality of light-emitting regions, e.g. multi-junction LEDs or light-emitting devices having photoluminescent regions within the bodies - H01S 5/34: comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers (H01S5/36 takes precedence) - H10H 20/0137: {the light-emitting regions comprising nitride materials} - H10H 20/815: having stress relaxation structures, e.g. buffer layers - H10H 20/821: of the light-emitting regions, e.g. non-planar junctions - H10H 20/825: containing nitrogen, e.g. GaN - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS - H01S: DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL ## Abstract The present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes an N-type semiconductor layer provided on a substrate in a vertical direction, and at least one of multiple-quantum-well structure is formed on the N-type semiconductor layer in a horizontal direction, a P-type semiconductor layer is provided above the multiple-quantum-well structure and on at least part of sides of the multiple-quantum-well structure, each multiple-quantum-well structure includes a plurality of semiconductor layers sequentially stacked in the vertical direction and a multiple-quantum-well unit formed between each two adjacent semiconductor layers of the plurality of semiconductor layers, and the P-type semiconductor layer is in contact with each of the plurality of semiconductor layers of the multiple-quantum-well structure in the vertical direction. The method is used to manufacture the semiconductor structure. ## Claims ### Claim 1 A semiconductor structure, comprising: a substrate; an N-type semiconductor layer on the substrate; a multiple-quantum-well structure provided on the N-type semiconductor layer, wherein the multiple-quantum-well structure comprises a plurality of semiconductor layers sequentially stacked and a multiple-quantum-well unit formed between each two adjacent semiconductor layers of the plurality of semiconductor layers; wherein for each of the plurality of semiconductor layers of the multiple-quantum-well structure, the semiconductor layer comprises a first semiconductor sub-layer and a second semiconductor sub-layer periodically stacked, and the multiple-quantum-well unit is between the first semiconductor sub-layer and the second semiconductor sub-layer; wherein the first semiconductor sub-layer comprises indium, and the indium in the first semiconductor sub-layer of each of the plurality of semiconductor layers of the multiple-quantum-well structure has a different molar content of indium; and a P-type semiconductor layer on the multiple-quantum-well structure and on at least part of sides of the multiple-quantum-well structure, wherein the P-type semiconductor layer is in contact with each of the plurality of semiconductor layers of the multiple-quantum-well structure. ### Claim 2 (depends on 1) The semiconductor structure of claim 1, wherein the N-type semiconductor layer is provided with a groove penetrating through the N-type semiconductor layer, and a multiple-quantum-well structure is formed in the groove. ### Claim 3 (depends on 1) The semiconductor structure of claim 1, wherein the multiple-quantum-well structures is singular or plural in number, when the multiple-quantum-well structures is plural in number, a plurality of multiple-quantum-well structures are regularly or irregularly arranged along a horizontal direction. ### Claim 4 (depends on 1) The semiconductor structure of claim 1, wherein a molar content of indium in the first semiconductor sub-layers of the plurality of semiconductor layers increases sequentially along a direction of the N-type semiconductor layer pointing toward the P-type semiconductor layer. ### Claim 5 (depends on 4) The semiconductor structure of claim 4, wherein materials of the first semiconductor sub-layers of the plurality of semiconductor layers comprise InGaN, and materials of the second semiconductor sub-layers of the plurality of semiconductor layers comprise GaN; a material of the N-type semiconductor layer comprises a group III nitride; a material of the P-type semiconductor layer comprises a group Ill nitride. ### Claim 6 (depends on 1) The semiconductor structure of claim 1, further comprising: an intrinsic semiconductor layer between the substrate and the N-type semiconductor layer. ### Claim 7 (depends on 1) The semiconductor structure of claim 1, further comprising: a stress-release layer between the N-type semiconductor layer and the multiple-quantum-well structure. ### Claim 8 (depends on 7) The semiconductor structure of claim 7, wherein a material of the stress-release layer comprises at least one of GaN or InGaN. ### Claim 9 (depends on 1) The semiconductor structure of claim 1, further comprising a dielectric layer between the N-type semiconductor layer and the P-type semiconductor layer, the dielectric layer is formed with a hollow out region, and the multiple-quantum-well structure is formed in the hollow out region. ### Claim 10 (depends on 1) The semiconductor structure of claim 1, wherein the sides of the multiple-quantum-well structure extend obliquely inward along the direction of the N-type semiconductor layer pointing toward the P-type semiconductor layer, and the sides are oblique or curved. ### Claim 11 (depends on 1) The semiconductor structure of claim 1, wherein each of the plurality of semiconductor layers of the multiple-quantum-well structure emits light at a different emission wavelength, wherein the semiconductor layer closest to the N-type semiconductor layer has the shortest emission wavelength, and the semiconductor layer farthest from the N-type semiconductor layer has the longest emission wavelength. ### Claim 12 A method for manufacturing a semiconductor structure, comprising: S1: forming an N-type semiconductor layer on a substrate in a vertical direction to form an intermediate semiconductor structure; S2: forming a multiple-quantum-well structure on the intermediate semiconductor structure, wherein the multiple-quantum-well structure comprises a plurality of semiconductor layers sequentially stacked and a multiple-quantum-well unit formed between each two adjacent semiconductor layers of the plurality of semiconductor layers; wherein for each of the plurality of semiconductor layers of the multiple-quantum-well structure, the semiconductor layer comprises a first semiconductor sub-layer and a second semiconductor sub-layer periodically stacked, and the multiple-quantum-well unit is between the first semiconductor sub-layer and the second semiconductor sub-layer; wherein the first semiconductor sub-layer comprises indium, and the indium in the first semiconductor sub-layer of each of the plurality of semiconductor layers of the multiple-quantum-well structure has a different molar content of indium; and S3: forming a P-type semiconductor layer on the multiple-quantum-well structure and on at least part of sides of the multiple-quantum-well structure, wherein the P-type semiconductor layer is in contact with each of the plurality of semiconductor layers of the multiple-quantum-well structure in the vertical direction. ### Claim 13 (depends on 12) The method of claim 12, wherein the step S2 comprises: S21: forming a multiple-quantum-well layer on the intermediate semiconductor structure; S22: forming a mask on the multiple-quantum-well layer; S23: etching or corroding the multiple-quantum-well layer through the mask to form the multiple-quantum-well structure; and S24: removing the mask. ### Claim 14 (depends on 12) The method of claim 12, wherein the step S2 comprises: S21: forming a mask on the intermediate semiconductor structure; S22: forming the multiple-quantum-well structure in a hollow out region of the mask; and S23: removing the mask. ### Claim 15 (depends on 12) The method of claim 12, wherein the step S2 comprises: S21: forming a dielectric layer and a mask stacked on the intermediate semiconductor structure; S22: forming the multiple-quantum-well structure in a hollow out region of the mask and in a hollow out region of the dielectric layer, and the hollow out region of the mask is formed corresponding to the hollow out region of the dielectric layer; and S23: removing the mask. ### Claim 16 (depends on 12) The method of claim 12, wherein the step S2 comprises: S21: forming a groove on the intermediate semiconductor structure; and S22: forming a multiple-quantum-well structure on the intermediate semiconductor structure and in the groove. ### Claim 17 (depends on 12) The method of claim 12, wherein the step S1 comprises: S11: forming an intrinsic semiconductor layer on the substrate; S12: forming the N-type semiconductor layer on the intrinsic semiconductor layer; and S13: forming a stress-release layer on the N-type semiconductor layer to form the intermediate semiconductor structure. ### Claim 18 (depends on 13) The method of claim 13, wherein a depth of etching or corroding of the multiple-quantum-well layer in the step S23 is equal to or less than a thickness of the multiple-quantum-well layer.