# US 12,604,532 B2 · Silicon controlled rectifiers

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- Number: US 12,604,532 B2
- Document ID: US12604532B2
- Status: Granted
- Kind: B2
- Application number: 18/300,161
- Filed: 2023-04-13
- Published: 2024-10-17
- Granted: 2026-04-14
- Earliest claimed: 2023-04-13
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GlobalFoundries U.S. Inc.
- Inventors: Anindya Nath; Rajendran Krishnasamy; Souvick Mitra; Steven M. Shank; Sagar P. Karalkar
- Web page: https://patentgrep.com/patent/US12604532B2

## CPC

- H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices}
- H10D 8/605: {of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure relates to semiconductor structures and, more particularly, to silicon control rectifiers and methods of manufacture. A structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; a plurality of shallow trench isolation structures extending into the first well and the second well; and at least one gate structure in the first well which abuts one shallow trench isolation structure of the plurality of shallow trench isolation structures.

## Claims

### Claim 1

A structure comprising:
a first well in a semiconductor substrate;
a second well in the semiconductor substrate, adjacent to the first well;
a plurality of shallow trench isolation structures extending into the first well and the second well; and
at least one gate structure in the first well which abuts one shallow trench isolation structure of the plurality of shallow trench isolation structures,
wherein the at least one gate structure is within the first well.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the first well comprises a P-well and the second well comprises an N-well.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the first well comprises an N-well and the second well comprises a P-well.

### Claim 4 (depends on 1)

The structure of claim 1, wherein the at least one gate structure comprises at least one vertical gate structure extending between an anode and a cathode.

### Claim 5 (depends on 1)

The structure of claim 1, wherein the at least one gate structure comprises at least one vertical gate structure extending below a bottom surface of the first well.

### Claim 6 (depends on 1)

The structure of claim 1, wherein the at least one gate structure comprises at least one vertical gate structure extending to a same depth as the plurality of shallow trench isolation structures.

### Claim 7 (depends on 1)

The structure of claim 1, wherein the at least one gate structure comprises a plurality of gate structures within the first well.

### Claim 8 (depends on 7)

The structure of claim 7, further comprising a first current path between the plurality of gate structures and a second current path under the plurality of gate structures.

### Claim 9 (depends on 1)

The structure of claim 1, wherein the at least one gate structure comprises a single gate structure and a single current path is under the single gate structure.

### Claim 10 (depends on 9)

The structure of claim 9, wherein the at least one gate structure is along a width of the first well.

### Claim 11 (depends on 1)

The structure of claim 1, wherein the at least one gate structure is remotely positioned from the second well.

### Claim 12 (depends on 1)

The structure of claim 1, wherein the at least one gate structure comprises polysilicon material with a trench in the semiconductor substrate.

### Claim 13 (depends on 1)

The structure of claim 1, further comprising diffusion regions in the first well and the second well, wherein the plurality of shallow trench isolation structures extending into the first well and the second well isolate the diffusion regions.

### Claim 14

A structure comprising:
a first well in a semiconductor substrate and electrically coupled to an anode;
a second well in the semiconductor substrate and electrically coupled to a cathode; and
at least one vertical gate structure extending vertically within the semiconductor substrate and which sits between the anode and the cathode,
wherein the at least one vertical gate structure comprises a plurality of vertical gate structures sitting within the second well.

### Claim 15 (depends on 14)

The structure of claim 14, further comprising at least one shallow trench isolation structure abutting the plurality of vertical gate structures.

### Claim 16 (depends on 15)

The structure of claim 15, wherein the second well comprises a P+ well and the first well comprises an N+ well abutting the P+ well.

### Claim 17 (depends on 16)

The structure of claim 16, wherein the plurality of gate structures extend through the P+ well.

### Claim 18 (depends on 14)

The structure of claim 14, wherein the second well comprises an N-well.

### Claim 19

A method comprising:
forming a first well in a semiconductor substrate;
forming a second well in the semiconductor substrate, adjacent to the first well;
forming a plurality of shallow trench isolation structures extending into the first well and the second well; and
forming at least one vertical gate structure in the first well which abuts one shallow trench isolation structure of the plurality of shallow trench isolation structures, and below a bottom surface of the first well.