# US 12,604,531 B2 · Standard cell architecture without power delivery space allocation

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- Number: US 12,604,531 B2
- Document ID: US12604531B2
- Status: Granted
- Kind: B2
- Application number: 17/561,693
- Filed: 2021-12-23
- Published: 2023-06-29
- Granted: 2026-04-14
- Earliest claimed: 2021-12-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Sukru Yemenicioglu; Richard E. Schenker; Xinning Wang; Mauro J. Kobrinsky; Tahir Ghani
- Web page: https://patentgrep.com/patent/US12604531B2

## CPC

- H10D 89/10: Integrated device layouts
- G06F 30/394: Routing (G06F30/396 takes precedence)
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/427: {Power or ground buses}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/981: {Power supply lines}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to standard cell architectures without power delivery space allocation. Other embodiments may be described or claimed.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a first transistor on a front side of a wafer;
a second transistor on the front side of the wafer and adjacent to the first transistor along a gate direction, wherein there are no power delivery tracks on the front side of the wafer electrically coupled to the first or second transistor, and wherein there is no boundary deep via between the first and second transistor;
a first pair of signal metal routing tracks coupled to the first transistor on the front side of the wafer;
a first single signal metal routing track coupled to the second transistor on the front side of the wafer, wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor;
a third transistor on the front side of a wafer and adjacent to the second transistor along the gate direction;
a fourth transistor on the front side of the wafer and adjacent to the third transistor along the gate direction, wherein there are no power delivery tracks on the front side of the wafer electrically coupled to the third or fourth transistor, and wherein there is no boundary deep via between the third and fourth transistor;
a second pair of signal metal routing tracks coupled to the third transistor on the front side of the wafer; and
a second single signal metal routing track coupled to the fourth transistor on the front side of the wafer, wherein the third transistor is a PMOS transistor and the fourth transistor is an NMOS transistor.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the first transistor is included within a first cell height (CH) and the second transistor is included within a second CH.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, further comprising a device distance between the first transistor and the second transistor, wherein the device distance is not based on a process margin distance associated with a metal power-delivery structure.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, wherein the first pair of signal metal routing tracks and the first single signal metal routing track do not provide a power or ground connection to the first and second transistors.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, further comprising a power delivery track on a back side of the wafer and electrically coupled to the first or second transistor, the back side of the wafer opposite the front side of the wafer.

### Claim 6

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first transistor on a front side of a wafer;
a second transistor on the front side of the wafer and adjacent to the first transistor along a gate direction, wherein there are no power delivery tracks on the front side of the wafer electrically coupled to the first or second transistor, and wherein there is no boundary deep via between the first and second transistor;
a first pair of signal metal routing tracks coupled to the first transistor on the front side of the wafer;
a first single signal metal routing track coupled to the second transistor on the front side of the wafer, wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor;
a third transistor on the front side of a wafer and adjacent to the second transistor along the gate direction;
a fourth transistor on the front side of the wafer and adjacent to the third transistor along the gate direction, wherein there are no power delivery tracks on the front side of the wafer electrically coupled to the third or fourth transistor, and wherein there is no boundary deep via between the third and fourth transistor;
a second pair of signal metal routing tracks coupled to the third transistor on the front side of the wafer; and
a second single signal metal routing track coupled to the fourth transistor on the front side of the wafer, wherein the third transistor is a PMOS transistor and the fourth transistor is an NMOS transistor.

### Claim 7 (depends on 6)

The computing device of claim 6, further comprising: a processor coupled to the board, a communication chip coupled to the board, or a camera coupled to the board.

### Claim 8

An integrated circuit structure, comprising:
a first transistor on a front side of a wafer,
a second transistor on the front side of the wafer and adjacent to the first transistor along a gate direction, wherein there are no power delivery tracks on the front side of the wafer electrically coupled to the first or second transistor, and wherein there is no boundary deep via between the first and second transistor;
a first pair of signal metal routing tracks coupled to the first transistor on the front side of the wafer;
a first single signal metal routing track coupled to the second transistor on the front side of the wafer, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor;
a third transistor on the front side of a wafer and adjacent to the second transistor along the gate direction;
a fourth transistor on the front side of the wafer and adjacent to the third transistor along the gate direction, wherein there are no power delivery tracks on the front side of the wafer electrically coupled to the third or fourth transistor, and wherein there is no boundary deep via between the third and fourth transistor;
a second pair of signal metal routing tracks coupled to the third transistor on the front side of the wafer; and
a second single signal metal routing track coupled to the fourth transistor on the front side of the wafer, wherein the third transistor is an NMOS transistor and the fourth transistor is a PMOS transistor.

### Claim 9 (depends on 8)

The integrated circuit structure of claim 8, wherein the first transistor is included within a first cell height (CH) and the second transistor is included within a second CH.

### Claim 10 (depends on 8)

The integrated circuit structure of claim 8, further comprising a device distance between the first transistor and the second transistor, wherein the device distance is not based on a process margin distance associated with a metal power-delivery structure.

### Claim 11 (depends on 8)

The integrated circuit structure of claim 8, wherein the first pair of signal metal routing tracks and the first single signal metal routing track do not provide a power or ground connection to the first and second transistors.

### Claim 12 (depends on 8)

The integrated circuit structure of claim 8, further comprising a power delivery track on a back side of the wafer and electrically coupled to the first or second transistor, the back side of the wafer opposite the front side of the wafer.

### Claim 13

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first transistor on a front side of a wafer;
a second transistor on the front side of the wafer and adjacent to the first transistor along a gate direction, wherein there are no power delivery tracks on the front side of the wafer electrically coupled to the first or second transistor, and wherein there is no boundary deep via between the first and second transistor;
a first pair of signal metal routing tracks coupled to the first transistor on the front side of the wafer;
a first single signal metal routing track coupled to the second transistor on the front side of the wafer, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor;
a third transistor on the front side of a wafer and adjacent to the second transistor along the gate direction;
a fourth transistor on the front side of the wafer and adjacent to the third transistor along the gate direction, wherein there are no power delivery tracks on the front side of the wafer electrically coupled to the third or fourth transistor, and wherein there is no boundary deep via between the third and fourth transistor;
a second pair of signal metal routing tracks coupled to the third transistor on the front side of the wafer; and
a second single signal metal routing track coupled to the fourth transistor on the front side of the wafer, wherein the third transistor is an NMOS transistor and the fourth transistor is a PMOS transistor.

### Claim 14 (depends on 13)

The computing device of claim 13, further comprising: a processor coupled to the board, a communication chip coupled to the board, or a camera coupled to the board.