# US 12,604,521 B2 · Semiconductor device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,521 B2 - Document ID: US12604521B2 - Status: Granted - Kind: B2 - Application number: 18/150,545 - Filed: 2023-01-05 - Published: 2024-06-13 - Granted: 2026-04-14 - Earliest claimed: 2022-12-11 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Wei-Chih Hou; Chun-Jun Lin; Feng-Ming Chang; Shu-Ning Hsu - Web page: https://patentgrep.com/patent/US12604521B2 ## CPC - H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS} - H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 62/121: {oriented parallel to substrates} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 84/0167: {Manufacturing their channels} - H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions} - H10D 84/0188: {Manufacturing their isolation regions} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/8311: {the IGFETs characterised by having different channel structures} - H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions} - H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors} - H10D 84/852: {comprising forksheet IGFETs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method includes depositing an epitaxial stack over a substrate, the epitaxial stack comprising alternating first semiconductor layers and second semiconductor layers, wherein the first semiconductor layers comprise a different semiconductor composition from that of the second semiconductor layers; forming a dielectric wall in the epitaxial stack; removing a first subset of the first semiconductor layers on a first side of the dielectric wall, while leaving a first subset of the second semiconductor layers on the first side of the dielectric wall; removing a second subset of the second semiconductor layers on a second side of the dielectric wall, while leaving a second subset of the first semiconductor layers on the second side of the dielectric wall; forming a first gate structure around the first subset of the second semiconductor layers; and forming a second gate structure around the second subset of the first semiconductor layers. ## Claims ### Claim 1 A method, comprising: depositing an epitaxial stack over a substrate, the epitaxial stack comprising alternating first semiconductor layers and second semiconductor layers, wherein the first semiconductor layers comprise a different semiconductor composition from that of the second semiconductor layers; forming a dielectric wall in the epitaxial stack; removing a first subset of the first semiconductor layers on a first side of the dielectric wall, while leaving a first subset of the second semiconductor layers on the first side of the dielectric wall; removing a second subset of the second semiconductor layers on a second side of the dielectric wall, while leaving a second subset of the first semiconductor layers on the second side of the dielectric wall; forming a first isolation structure over the substrate and having a top surface lower than a top surface of the dielectric wall, wherein the first semiconductor layers are between the dielectric wall and the first isolation structure; forming a second isolation structure over the substrate and having a top surface lower than the top surface of the dielectric wall, wherein the second semiconductor layers are between the dielectric wall and the second isolation structure, and the top surface of the first isolation structure is higher than the top surface of the second isolation structure; forming a first gate structure around the first subset of the second semiconductor layers; and forming a second gate structure around the second subset of the first semiconductor layers. ### Claim 2 (depends on 1) The method of claim 1, further comprising: forming an n-type source/drain epitaxial structure interfacing the first subset of the second semiconductor layers; and forming a p-type source/drain epitaxial structure interfacing the second subset of the first semiconductor layers. ### Claim 3 (depends on 2) The method of claim 2, wherein a bottom surface of the n-type source/drain epitaxial structure is higher than a bottom surface of the p-type source/drain epitaxial structure. ### Claim 4 (depends on 1) The method of claim 1, wherein depositing the epitaxial stack is performed such that a thickness of the second semiconductor layers is greater than a thickness of the first semiconductor layers. ### Claim 5 (depends on 1) The method of claim 1, wherein a Ge concentration in the first semiconductor layers is greater than a Ge concentration in the second semiconductor layers. ### Claim 6 (depends on 1) The method of claim 1, further comprising: forming a plurality of spacers on the first subset of the first semiconductor layers and on the second subset of the second semiconductor layers prior to removing the first subset of the first semiconductor layers and the second subset of the second semiconductor layers. ### Claim 7 (depends on 1) The method of claim 1, further comprising: depositing a liner layer over the epitaxial stack prior to forming the dielectric wall in the epitaxial stack. ### Claim 8 (depends on 7) The method of claim 7, further comprising: etching the liner layer such that the liner layer has a top surface level with a top surface of the epitaxial stack. ### Claim 9 (depends on 7) The method of claim 7, wherein the liner layer comprises semiconductor oxide material. ### Claim 10 A method, comprising: depositing an epitaxial stack over a substrate, the epitaxial stack comprising a first semiconductor layer, a second semiconductor layer, and alternating third semiconductor layers and fourth semiconductor layers, wherein the first and third semiconductor layers comprise a different semiconductor composition from that of the second and fourth semiconductor layers; patterning the epitaxial stack into a first fin and a second fin, wherein the first fin comprises a first portion of the first semiconductor layer, a first portion of the second semiconductor layer, a first subset of the third semiconductor layers and a first subset of the fourth semiconductor layers, and the second fin comprises a second portion of the first semiconductor layer, a second portion of the second semiconductor layer, a second subset of the third semiconductor layers and a second subset of the fourth semiconductor layers; forming a dielectric wall between the first and second fins; forming a first isolation structure over the substrate and having a top surface lower than a top surface of the dielectric wall, wherein the first fin is between the dielectric wall and the first isolation structure; forming a second isolation structure over the substrate and having a top surface lower than the top surface of the dielectric wall, wherein the second fin is between the dielectric wall and the second isolation structure, and the top surface of the first isolation structure is higher than the top surface of the second isolation structure; replacing the first subset of the third semiconductor layers with a first gate structure; and replacing the second portion of the second semiconductor layer and the second subset of the fourth semiconductor layers with a second gate structure. ### Claim 11 (depends on 10) The method of claim 10, wherein replacing the first subset of the third semiconductor layers with the first gate structure is performed such that the first gate structure is over the first portion of the first semiconductor layer and the first portion of the second semiconductor layer. ### Claim 12 (depends on 10) The method of claim 10, wherein replacing the second portion of the second semiconductor layer and the second subset of the fourth semiconductor layers with the second gate structure is performed such that the second gate structure is over the second portion of the first semiconductor layer. ### Claim 13 (depends on 10) The method of claim 10, wherein the first semiconductor layer is thicker than the third semiconductor layers, and the second semiconductor layer is thicker than the fourth semiconductor layers. ### Claim 14 (depends on 10) The method of claim 10, further comprises: etching a first source/drain opening in the first fin until reaching the first portion of the second semiconductor layer; epitaxial growing a first source/drain epitaxial structure from the first portion of the second semiconductor layer and the first subset of the fourth semiconductor layers; etching a second source/drain opening in the second fin until reaching the second portion of the first semiconductor layer; and epitaxial growing a second source/drain epitaxial structure from the second portion of the first semiconductor layer and the second subset of the third semiconductor layers. ### Claim 15 (depends on 10) The method of claim 10, wherein the top surface of the first isolation structure is laterally aligned with the second semiconductor layer, and the top surface of the second isolation structure is laterally aligned with the first semiconductor layer. ### Claim 16 (depends on 10) The method of claim 10, wherein forming the dielectric wall comprises: depositing a dielectric material over and between the first and second fins; and etching back the dielectric material. ### Claim 17 (depends on 10) The method of claim 10, further comprises: conformally depositing a liner layer over and between the first and second fins prior to forming the dielectric wall. ### Claim 18 (depends on 17) The method of claim 17, wherein forming the dielectric wall is performed such that a top end of the liner layer is lowered to a position level with or higher than a top surface of the epitaxial stack, and the dielectric wall is in contact with the top end of the liner layer. ### Claim 19 A method, comprising: forming a dielectric wall on a substrate; forming a plurality of first semiconductor channels on a first side of the dielectric wall; forming a plurality of second semiconductor channels on a second side of the dielectric wall, wherein the second semiconductor channels comprise a different semiconductor composition from that of the first semiconductor channels, and the first semiconductor channels are misaligned with the second semiconductor channels in a cross-sectional view; forming a first isolation structure over the substrate and having a top surface lower than a top surface of the dielectric wall, wherein the first semiconductor channels are between the dielectric wall and the first isolation structure; forming a second isolation structure over the substrate and having a top surface lower than the top surface of the dielectric wall, wherein the second semiconductor channels are between the dielectric wall and the second isolation structure, and the top surface of the first isolation structure is higher than the top surface of the second isolation structure; forming a gate structure wrapping around the first semiconductor channels; and forming a second gate structure wrapping around the second semiconductor channels. ### Claim 20 (depends on 19) The method of claim 19, further comprising: growing an n-type source/drain epitaxial structure interfacing the first semiconductor channels; and growing a p-type source/drain epitaxial structure interfacing the second semiconductor channels.