# US 12,604,515 B2 · Semiconductor device structure with inner spacer layer

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- Number: US 12,604,515 B2
- Document ID: US12604515B2
- Status: Granted
- Kind: B2
- Application number: 18/477,055
- Filed: 2023-09-28
- Published: 2024-01-18
- Granted: 2026-04-14
- Earliest claimed: 2019-09-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ching-Wei Tsai; Yu-Xuan Huang; Kuan-Lun Cheng; Chih-Hao Wang; Min Cao; Jung-Hung Chang; Lo-Heng Chang; Pei-Hsun Wang; Kuo-Cheng Chiang
- Web page: https://patentgrep.com/patent/US12604515B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/508: {characterised by the relative sizes, shapes or dispositions of the inner spacers}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10P 14/3462: {Nanowires}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base. The semiconductor device structure includes a first multilayer stack over the base. The first multilayer stack includes a first channel layer and a second channel layer over and spaced apart from the first channel layer. The semiconductor device structure includes a gate stack over the substrate. The gate stack wraps around the first multilayer stack. The semiconductor device structure includes an inner spacer layer between the second channel layer and the first channel layer and between the first channel layer and the base. The semiconductor device structure includes a bottom spacer over the base. The semiconductor device structure includes a first source/drain structure over the bottom spacer and connected to the second channel layer.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a substrate having a base;
a first multilayer stack over the base, wherein the first multilayer stack comprises a first channel layer and a second channel layer over and spaced apart from the first channel layer;
a gate stack over the substrate, wherein the gate stack wraps around the first multilayer stack;
an inner spacer layer between the second channel layer and the first channel layer and between the first channel layer and the base;
a bottom spacer over the base, wherein a bottom of the inner spacer layer is located vertically between a top of the bottom spacer and a bottom of the bottom spacer; and
a first source/drain structure over the bottom spacer and connected to the second channel layer, wherein the bottom spacer separates the first source/drain structure from the base, and the bottom spacer and the inner spacer layer are made of a same material.

### Claim 2 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the bottom spacer is connected to the inner spacer layer.

### Claim 3 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the first source/drain structure extends into the bottom spacer.

### Claim 4 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a second multilayer stack over the base, wherein the gate stack further wraps around the second multilayer stack, and the second multilayer stack is wider than the first multilayer stack.

### Claim 5 (depends on 4)

The semiconductor device structure as claimed in claim 4, further comprising:
a second source/drain structure connected to the second multilayer stack, wherein the second source/drain structure is wider than the first source/drain structure.

### Claim 6 (depends on 5)

The semiconductor device structure as claimed in claim 5, wherein the substrate has a first fin structure and a second fin structure over the base, the first fin structure comprises a first bottom portion, the first multilayer stack is over the first bottom portion, the second fin structure comprises a second bottom portion, the second multilayer stack is over the second bottom portion, the bottom spacer separates the first source/drain structure from the first bottom portion, and the second source/drain structure is over the second bottom portion.

### Claim 7 (depends on 6)

The semiconductor device structure as claimed in claim 6, wherein the second source/drain structure is in direct contact with the second bottom portion.

### Claim 8 (depends on 6)

The semiconductor device structure as claimed in claim 6, wherein the bottom spacer extends into the first bottom portion.

### Claim 9

A semiconductor device structure, comprising:
a substrate having a base;
a multilayer stack over the base, wherein the multilayer stack comprises a first channel layer and a second channel layer over and spaced apart from the first channel layer;
a gate stack over the substrate, wherein the gate stack wraps around the multilayer stack;
an inner spacer layer between the second channel layer and the first channel layer and between the first channel layer and the base;
a bottom spacer over the base and covering a first sidewall of the first channel layer, wherein a portion of the inner spacer layer is located between the bottom spacer and a side edge of the first channel layer; and
a source/drain structure over the bottom spacer and connected to the second channel layer, wherein the source/drain structure is electrically insulated from the first channel layer.

### Claim 10 (depends on 9)

The semiconductor device structure as claimed in claim 9, wherein the bottom spacer and the inner spacer layer together form a continuous structure.

### Claim 11 (depends on 9)

The semiconductor device structure as claimed in claim 9, wherein the inner spacer layer continuously covers the first sidewall of the first channel layer, a second sidewall of the gate stack, and a top surface of the base.

### Claim 12 (depends on 11)

The semiconductor device structure as claimed in claim 11, wherein the bottom spacer is embedded in the inner spacer layer.

### Claim 13

A semiconductor device structure, comprising:
a substrate;
a multilayer stack over the substrate, wherein the multilayer stack comprises a first channel layer and a second channel layer over and spaced apart from the first channel layer;
a gate stack over the substrate, wherein the gate stack wraps around the multilayer stack;
an inner spacer layer between the second channel layer and the first channel layer and between the first channel layer and the substrate and covering a sidewall of the first channel layer, wherein the inner spacer layer has a concave top surface facing away from the substrate, and the inner spacer layer extends upwards along a side edge of the first channel layer; and
a source/drain structure over the inner spacer layer and connected to the second channel layer, wherein the source/drain structure is electrically insulated from the first channel layer.

### Claim 14 (depends on 13)

The semiconductor device structure as claimed in claim 13, further comprising:
a bottom spacer between the inner spacer layer and the source/drain structure.

### Claim 15 (depends on 14)

The semiconductor device structure as claimed in claim 14, wherein the bottom spacer is embedded in the inner spacer layer.

### Claim 16 (depends on 15)

The semiconductor device structure as claimed in claim 15, wherein the bottom spacer has a curved bottom surface.

### Claim 17 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein the concave top surface of the inner spacer layer is a concave curved surface.

### Claim 18 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the bottom spacer has a curved sidewall surface extending upwards along a sidewall of the inner spacer layer and a side edge of the first channel layer.

### Claim 19 (depends on 9)

The semiconductor device structure as claimed in claim 9, wherein the inner spacer layer laterally extends across opposite edges of the bottom spacer.

### Claim 20 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein inner spacer layer laterally surrounds the bottom spacer.