# US 12,604,514 B2 · Semiconductor device with recessed gate and method for fabricating the same

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- Number: US 12,604,514 B2
- Document ID: US12604514B2
- Status: Granted
- Kind: B2
- Application number: 18/239,874
- Filed: 2023-08-30
- Published: 2025-03-06
- Granted: 2026-04-14
- Earliest claimed: 2023-08-30
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Ying-Cheng Chuang
- Web page: https://patentgrep.com/patent/US12604514B2

## CPC

- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D 89/10: Integrated device layouts
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a first peripheral region and a second peripheral region; a plurality of recessed gates respectively including a recessed gate dielectric layer inwardly positioned in the first peripheral region and including a U-shaped cross-sectional profile, a recessed gate bottom conductive layer positioned on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile, resulting in a first valley, a recessed gate top conductive layer conformally positioned on the first valley of the recessed gate bottom conductive layer, and a recessed gate capping layer positioned on the recessed gate top conductive layer; and a peripheral gate structure positioned on the second peripheral region. An element density of the first peripheral region is greater than an element density of the second peripheral region.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate comprising a first peripheral region and a second peripheral region;
a plurality of recessed gates respectively comprising:
a recessed gate dielectric layer inwardly positioned in the first peripheral region and comprising a U-shaped cross-sectional profile;
a recessed gate bottom conductive layer positioned on the recessed gate dielectric layer and comprising a valley-shaped cross-sectional profile, resulting in a first valley;
a recessed gate top conductive layer conformally positioned on the first valley of the recessed gate bottom conductive layer; and
a recessed gate capping layer positioned on the recessed gate top conductive layer; and
a peripheral gate structure positioned on the second peripheral region;
wherein an element density of the first peripheral region is greater than an element density of the second peripheral region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the peripheral gate structure comprises:
a gate dielectric layer positioned on the second peripheral region;
a gate bottom conductive layer positioned on the gate dielectric layer;
a gate top conductive layer positioned on the gate bottom conductive layer; and
a gate capping layer positioned on the gate top conductive layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein a width of the gate dielectric layer is greater than a width of the recessed gate dielectric layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the gate dielectric layer and the recessed gate dielectric layer comprise the same material.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the gate bottom conductive layer and the recessed gate bottom conductive layer comprise the same material.

### Claim 6 (depends on 3)

The semiconductor device of claim 3, wherein the gate top conductive layer and the recessed gate top conductive layer comprise the same material.

### Claim 7 (depends on 3)

The semiconductor device of claim 3, wherein the gate capping layer and the recessed gate capping layer comprise the same material.