# US 12,604,511 B2 · Semiconductor device with active portions of varied widths inside active pattern

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,604,511 B2
- Document ID: US12604511B2
- Status: Granted
- Kind: B2
- Application number: 18/501,354
- Filed: 2023-11-03
- Published: 2024-11-21
- Granted: 2026-04-14
- Earliest claimed: 2023-05-17
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Joongwon Jeon; Kiheung Park; Jae Hyun Kang; Byung-Moo Kim
- Web page: https://patentgrep.com/patent/US12604511B2

## CPC

- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure relates to semiconductor devices. One example semiconductor device comprises a substrate that includes a first active pattern, a first source/drain pattern, a second source/drain pattern, and a third source/drain pattern on the first active patter, a first separation structure between the first source/drain pattern and the second source/drain pattern, and a second separation structure between the second source/drain pattern and the third source/drain pattern. The first active pattern includes a first active portion that overlaps the first source/drain pattern, a second active portion that overlaps the second source/drain pattern, a third active portion that overlaps the third source/drain pattern, a first intervening portion between the first active portion and the second active portion, and a second intervening portion between the second active portion and the third active portion.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate that includes a first active pattern;
a first source/drain pattern, a second source/drain pattern, and a third source/drain pattern that are on the first active pattern;
a first separation structure between the first source/drain pattern and the second source/drain pattern; and
a second separation structure between the second source/drain pattern and the third source/drain pattern,
wherein the first active pattern includes:
a first active portion that overlaps the first source/drain pattern;
a second active portion that overlaps the second source/drain pattern;
a third active portion that overlaps the third source/drain pattern;
a first intervening portion between the first active portion and the second active portion; and
a second intervening portion between the second active portion and the third active portion,
wherein the first intervening portion overlaps the first separation structure,
wherein the second intervening portion overlaps the second separation structure,
wherein a first width of the first active portion is different from a second width of the second active portion,
wherein a third width of the third active portion is different from the second width, and
wherein each of the first, second, and third active portions has a first sidewall and a second sidewall that are disposed symmetrically with respect to a central line of the first active pattern.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein
the first width is less than the second width,
a first distance between the central line and the first sidewall of the first active portion is less than a second distance between the central line and the first sidewall of the second active portion, and
a third distance between the central line and the second sidewall of the first active portion is less than a fourth distance between the central line and the second sidewall of the second active portion.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein
the third width is greater than the second width,
a fifth distance between the central line and the first sidewall of the third active portion is greater than the third distance, and
a sixth distance between the central line and the second sidewall of the third active portion is greater than the fourth distance.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a first distance between the first sidewall of the first active portion and the first sidewall of the second active portion is a same as a second distance between the first sidewall of the third active portion and the first sidewall of the second active portion.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein a third distance between the second sidewall of the first active portion and the second sidewall of the second active portion is a same as a fourth distance between the second sidewall of the third active portion and the second sidewall of the second active portion.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first distance, the second distance, the third distance, and the fourth distance are a same as each other.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein
a first maximum width of the first source/drain pattern is different from a second maximum width of the second source/drain pattern, and
a third maximum width of the third source/drain pattern is different from the second maximum width.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first active contact connected to the first source/drain pattern;
a second active contact connected to the second source/drain pattern; and
a third active contact connected to the third source/drain pattern,
wherein a fourth width of the first active contact is different from a fifth width of the second active contact, and
wherein a sixth width of the third active contact is different from the fifth width.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein
the first width is less than the second width,
the second width is less than the third width,
the fourth width is less than the fifth width, and
the fifth width is less than the sixth width.

### Claim 10

A semiconductor device, comprising:
a substrate that includes a first active pattern and a second active pattern; and
a first separation structure and a second separation structure on the first active pattern and the second active pattern,
wherein the first active pattern includes:
a first intervening portion that overlaps the first separation structure;
a second intervening portion that overlaps the second separation structure;
a first active portion connected to the first intervening portion;
a second active portion connected to the first intervening portion and the second intervening portion; and
a third active portion connected to the second intervening portion,
wherein a first width of the first active portion is different from a second width of the second active portion,
wherein a third width of the third active portion is different from the second width,
wherein each of the first, second, and third active portions has a first sidewall that faces the second active pattern, and
wherein a first distance between the first sidewall of the first active portion and the first sidewall of the second active portion is a same as a second distance between the first sidewall of the second active portion and the first sidewall of the third active portion.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein
each of the first, second, and third active portions has a second sidewall opposite to the first sidewall, and
the second sidewalls of the first, second, and third active portions are coplanar with each other.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein
each of the first, second, and third active portions has a second sidewall opposite to the first sidewall, and
the first sidewall and the second sidewall of each of the first, second, and third active portions are disposed symmetrically with respect to a central line of the first active pattern.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the second active pattern includes:
a third intervening portion that overlaps the first separation structure;
a fourth intervening portion that overlaps the second separation structure;
a fourth active portion connected to the third intervening portion;
a fifth active portion connected to the third intervening portion and the fourth intervening portion; and
a sixth active portion connected to the fourth intervening portion,
wherein a fourth width of the fourth active portion is different from a fifth width of the fifth active portion,
wherein a sixth width of the sixth active portion is different from the fifth width, and
wherein each of the fourth, fifth, and sixth active portions has a first sidewall and a second sidewall that are disposed symmetrically with respect to a central line of the second active pattern.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein the first active pattern further includes:
a third intervening portion connected to the third active portion; and
a fourth active portion connected to the third intervening portion,
wherein a fourth width of the fourth active portion is different from the third width,
wherein the fourth active portion has a first sidewall that faces the second active pattern, and
wherein a third distance between the first sidewall of the fourth active portion and the first sidewall of the third active portion is a same as the first distance and the second distance.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein the first active pattern further includes:
a third intervening portion connected to the third active portion; and
a dummy portion connected to the third intervening portion,
wherein a fourth width of the dummy portion is different from the third width,
wherein the dummy portion has a first sidewall that faces the second active pattern, and
wherein a third distance between the first sidewall of the dummy portion and the first sidewall of the third active portion is greater than the first distance and the second distance.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, further comprising a dummy source/drain pattern that overlaps the dummy portion, and
wherein the dummy source/drain pattern is electrically floated.

### Claim 17 (depends on 10)

The semiconductor device of claim 10, further comprising:
a gate electrode that intersects the first active pattern; and
a gate dielectric layer between the first active pattern and the gate electrode, and
wherein each of the first distance and the second distance is greater than a thickness of the gate dielectric layer.

### Claim 18 (depends on 10)

The semiconductor device of claim 10, further comprising a power line adjacent to the second active pattern,
wherein each of the first, second, and third active portions has a second sidewall opposite to the first sidewall,
wherein a distance between the power line and the first sidewall of the first active portion is greater than a distance between the power line and the first sidewall of the second active portion, and
wherein a distance between the power line and the second sidewall of the first active portion is less than a distance between the power line and the second sidewall of the second active portion.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein
the distance between the power line and the first sidewall of the second active portion is greater than a distance between the power line and the first sidewall of the third active portion, and
the distance between the power line and the second sidewall of the second active portion is less than a distance between the power line and the second sidewall of the third active portion.

### Claim 20

A semiconductor device, comprising:
a substrate that includes a first active pattern;
a first source/drain pattern, a second source/drain pattern, a third source/drain pattern, and a dummy source/drain pattern that are on the first active pattern;
a first separation structure between the first source/drain pattern and the second source/drain pattern;
a second separation structure between the second source/drain pattern and the third source/drain pattern; and
a third separation structure between the third source/drain pattern and the dummy source/drain pattern,
wherein the first active pattern includes:
a first active portion that overlaps the first source/drain pattern;
a second active portion that overlaps the second source/drain pattern;
a third active portion that overlaps the third source/drain pattern;
a dummy portion that overlaps the dummy source/drain pattern;
a first intervening portion between the first active portion and the second active portion;
a second intervening portion between the second active portion and the third active portion; and
a third intervening portion between the third active portion and the dummy portion,
wherein the first intervening portion overlaps the first separation structure,
wherein the second intervening portion overlaps the second separation structure,
wherein the third intervening portion overlaps the third separation structure,
wherein each of the first active portion, the second active portion, the third active portion, and the dummy portion has a first sidewall and a second sidewall that are disposed symmetrically with respect to a central line of the first active pattern, and
wherein each of (i) a first distance between the first sidewall of the first active portion and the first sidewall of the second active portion and (ii) a second distance between the first sidewall of the second active portion and the first sidewall of the third active portion is less than a third distance between the first sidewall of the third active portion and the first sidewall of the dummy portion.