# US 12,604,510 B2 · Contact jumper for non-self aligned contact devices

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- Number: US 12,604,510 B2
- Document ID: US12604510B2
- Status: Granted
- Kind: B2
- Application number: 17/941,248
- Filed: 2022-09-09
- Published: 2024-03-14
- Granted: 2026-04-14
- Earliest claimed: 2022-09-09
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ruilong Xie; Julien Frougier; Min Gyu Sung; Heng Wu
- Web page: https://patentgrep.com/patent/US12604510B2

## CPC

- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/42: Vias, e.g. via plugs
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a first source/drain contact disposed between a first gate structure and a second gate structure, a dielectric cap disposed on the first source/drain contact, and a first gate contact disposed over the dielectric cap. The first gate contact connects the first gate structure with the second gate structure.

## Claims

### Claim 1

A semiconductor structure, comprising:
a first source/drain contact disposed between a first gate structure and a second gate structure;
a dielectric cap disposed on the first source/drain contact;
a first gate contact disposed over the dielectric cap, the first gate contact connecting the first gate structure with the second gate structure;
a third gate structure adjacent the first gate structure;
a second gate contact disposed on the third gate structure;
a first source/drain region disposed between the first gate structure and the second gate structure;
a second source/drain region disposed between the first gate structure and the third gate structure; and
a second source/drain contact disposed on the second source/drain region,
wherein the first source/drain contact is disposed on the first source/drain region; and
wherein the second gate contact is separated from the first gate contact by a dielectric layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric cap has a top surface extending above a top surface of the first gate structure and the second gate structure.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein a middle portion of the first gate contact is disposed over the dielectric cap.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the first gate contact comprises a first via disposed on the first gate structure and a second via disposed on the second gate structure.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein the first via and the second via of the first gate contact are disposed in a first interlayer dielectric layer, and the middle portion of the first gate contact is disposed in a second interlayer dielectric layer.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric cap has a top surface extending above a top surface of the first gate structure and the second gate structure, and a middle portion of the first gate contact is disposed over the dielectric cap.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a fourth gate structure adjacent the second gate structure;
a third source/drain region disposed between the fourth gate structure and the second gate structure; and
a third source/drain contact disposed on the third source/drain region.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric cap comprises a dielectric material selected from the group consisting of SiN, SiO2, SiOC, SiOCN, SiBCN and SiC.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the first source/drain region and the second source/drain region are disposed between a first stack of nanosheet channel layers.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the second source/drain region is disposed between the first stack of nanosheet channel layers and a second stack of nanosheet channel layers.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the first stack of nanosheet channel layers and the second stack of nanosheet channel layers are disposed on a bottom dielectric insulator layer.

### Claim 12

A semiconductor structure, comprising:
a first source/drain contact disposed between a first gate structure and a second gate structure;
a dielectric cap disposed on the first source/drain contact, the dielectric cap extending above a top surface of the first gate structure and the second gate structure;
a gate contact jumper connecting the first gate structure with the second gate structure, wherein a portion of the gate contact jumper is disposed over the dielectric cap:
a third gate structure adjacent the first gate structure; and
a gate contact disposed on the third gate structure;
a first source/drain region disposed between the first gate structure and the second gate structure;
a second source/drain region disposed between the first gate structure and the third gate structure; and
a second source/drain contact disposed on the second source/drain region;
wherein the first source/drain contact is disposed on the first source/drain region; and
wherein the gate contact is separated from the gate contact jumper by a dielectric layer.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein a middle portion of the gate contact jumper is disposed over the dielectric cap.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein the gate contact jumper comprises a first via disposed on the first gate structure and a second via disposed on the second gate structure.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, wherein the first via and the second via of the gate contact jumper are disposed in a first interlayer dielectric layer, and the middle portion of the gate contact jumper is disposed in a second interlayer dielectric layer.

### Claim 16 (depends on 12)

The semiconductor structure of claim 12, further comprising:
a fourth gate structure adjacent the second gate structure;
a third source/drain region disposed between the fourth gate structure and the second gate structure; and
a third source/drain contact disposed on the third source/drain region.

### Claim 17 (depends on 12)

The semiconductor structure of claim 12, wherein the dielectric cap comprises a dielectric material selected from the group consisting of SiN, SiO2, SiOC, SiOCN, SiBCN and SiC.

### Claim 18 (depends on 12)

The semiconductor structure of claim 12, wherein the first source/drain region and the second source/drain region are disposed between a first stack of nanosheet channel layers.

### Claim 19 (depends on 18)

The semiconductor structure of claim 18, wherein the second source/drain region is disposed between the first stack of nanosheet channel layers and a second stack of nanosheet channel layers.

### Claim 20 (depends on 19)

The semiconductor structure of claim 19, wherein the first stack of nanosheet channel layers and the second stack of nanosheet channel layers are disposed on a bottom dielectric insulator layer.