# US 12,604,508 B2 · Semiconductor device having side spacer patterns

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- Number: US 12,604,508 B2
- Document ID: US12604508B2
- Status: Granted
- Kind: B2
- Application number: 18/321,785
- Filed: 2023-05-23
- Published: 2024-05-02
- Granted: 2026-04-14
- Earliest claimed: 2022-11-01
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Young Gwang Yoon
- Web page: https://patentgrep.com/patent/US12604508B2

## CPC

- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes source/drain regions formed over a substrate, and channel patterns and gate structures formed between the source/drain regions in a horizontal direction. The channel patterns are arranged to be spaced apart from each other over a surface of the substrate in a vertical direction. The gate structures are disposed between the channel patterns in the vertical direction. The gate structures include the following: side spacer patterns formed adjacent to the source/drain regions in the first horizontal direction, interfacial insulating layers formed over upper and lower surfaces of the channel patterns, gate insulating layers over surfaces of the side spacer patterns and surfaces of the interfacial insulating layers, and gate electrodes over the gate insulating layers. The side spacer patterns include germanium (Ge).

## Claims

### Claim 1

A semiconductor device comprising:
source/drain regions formed over a substrate; and
channel patterns and gate structures formed between the source/drain regions in a horizontal direction,
wherein the channel patterns are arranged to be spaced apart from each other over a surface of the substrate in a vertical direction,
wherein the gate structures are disposed between the channel patterns in the vertical direction, and
wherein the gate structures include:
side spacer patterns formed adjacent to the source/drain regions in a first horizontal direction;
interfacial insulating layers formed over upper and lower surfaces of the channel patterns;
gate insulating layers formed over surfaces of the side spacer patterns and over surfaces of the interfacial insulating layers; and
gate electrodes over the gate insulating layers,
wherein the interfacial insulating layers include at least one of oxidized silicon or silicon oxide, and wherein the gate insulating layers include a high-k insulating material,
wherein the side spacer patterns include germanium (Ge),
wherein the gate insulating layers are in contact with the interfacial insulating layers in the vertical direction, and
wherein side end portions of the gate insulating layers are in contact with side surfaces of the side spacer patterns in the vertical direction.

### Claim 2 (depends on 1)

The semiconductor device of claim 1,
wherein the side spacer patterns include germanium-rich silicon germanium (SiGe).

### Claim 3 (depends on 1)

The semiconductor device of claim 1,
wherein the side spacer patterns include germanium-rich silicon germanium oxide (SiGeO).

### Claim 4 (depends on 1)

The semiconductor device of claim 1,
wherein each of the side spacer patterns includes:
a first side spacer pattern disposed adjacent to each of the source/drain regions; and
a second side spacer pattern disposed adjacent to the first side spacer pattern.

### Claim 5 (depends on 4)

The semiconductor device of claim 4,
wherein upper and lower end portions of the first side spacer pattern of each of the side spacer patterns are in contact with the channel patterns.

### Claim 6 (depends on 4)

The semiconductor device of claim 4,
wherein the first side spacer pattern of each of the side spacer patterns includes germanium (Ge).

### Claim 7 (depends on 4)

The semiconductor device of claim 4,
wherein the first side spacer pattern of each of the side spacer patterns has semiconductor characteristics.

### Claim 8 (depends on 4)

The semiconductor device of claim 4,
wherein the second side spacer pattern of each of the side spacer patterns includes germanium oxide (GeO).

### Claim 9 (depends on 1)

The semiconductor device of claim 1,
wherein side end portions of the interfacial insulating layers are in contact with at least one of upper end portions and lower end portions of the side spacer patterns in the first horizontal direction.

### Claim 10

A semiconductor device comprising:
source/drain regions formed over a substrate; and
channel patterns and gate structures formed between the source/drain regions in a horizontal direction,
wherein the channel patterns are arranged to be spaced apart from each other over a surface of the substrate,
wherein the gate structures are disposed between the channel patterns in the vertical direction,
wherein the gate structures include:
gate electrodes;
gate insulating layers surrounding the gate electrodes;
interfacial insulating layers surrounding the gate insulating layers; and
first side spacer patterns and second side spacer patterns between the gate insulating layers and the source/drain regions,
wherein inner surfaces of the second side spacer patterns are in contact with the gate insulating layers,
wherein:
the channel patterns include silicon (Si),
the first side spacer patterns include germanium (Ge), and
the second side spacer patterns include germanium oxide (GeO).

### Claim 11 (depends on 10)

The semiconductor device of claim 10,
wherein the first side spacer patterns include at least one of pure germanium (Ge) and germanium-rich silicon germanium (SiGe).

### Claim 12 (depends on 10)

The semiconductor device of claim 10,
wherein the second side spacer patterns include germanium-rich silicon germanium oxide (SiGeO).

### Claim 13 (depends on 10)

The semiconductor device of claim 10,
wherein side surfaces of the first side spacer patterns are in contact with the source/drain regions.

### Claim 14 (depends on 10)

The semiconductor device of claim 10,
wherein upper and lower end portions of the first side spacer patterns are in contact with the channel patterns.

### Claim 15 (depends on 10)

The semiconductor device of claim 10,
wherein upper and lower end portions of the second side spacer patterns are in contact with the interfacial insulating layers.

### Claim 16

A semiconductor device comprising:
source/drain regions formed over a substrate; and
channel patterns and gate structures formed between the source/drain regions in a horizontal direction,
wherein the channel patterns are arranged to be spaced apart from each other over a surface of the substrate in a vertical direction,
wherein the gate structures are disposed between the channel patterns in the vertical direction, and
wherein the gate structures include:
side spacer patterns formed adjacent to the source/drain regions in a first horizontal direction;
interfacial insulating layers formed over upper and lower surfaces of the channel patterns;
gate insulating layers formed over surfaces of the side spacer patterns and over surfaces of the interfacial insulating layers; and
gate electrodes over the gate insulating layers,
wherein:
the interfacial insulating layers includes a first material,
the gate insulating layers includes a second material different from the first material.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein:
the first material includes silicon, and
the second material includes metal.

### Claim 18 (depends on 16)

The semiconductor device of claim 16,
wherein inner surfaces of the side spacer patterns are in contact with the gate insulating layers.

### Claim 19 (depends on 16)

The semiconductor device of claim 16,
wherein upper and lower end portions of the side spacer patterns are in contact with the interfacial insulating layers.