# US 12,604,505 B2 · SiC trench MOSFET with an embedded junction barrier Schottky diode

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- Number: US 12,604,505 B2
- Document ID: US12604505B2
- Status: Granted
- Kind: B2
- Application number: 18/383,191
- Filed: 2023-10-24
- Published: 2025-04-24
- Granted: 2026-04-14
- Earliest claimed: 2023-10-24
- Assignees: Nami MOS CO., LTD.
- Applicants: Nami MOS CO., LTD.
- Inventors: Fu-Yuan Hsieh; Lin Xu
- Web page: https://patentgrep.com/patent/US12604505B2

## CPC

- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/8325: {Silicon carbide}
- H10D 8/60: Schottky-barrier diodes
- H10D 8/605: {of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]}
- H10D 12/031: {of IGBTs}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/146: {the built-in components being Schottky barrier diodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A SiC trench MOSFET with an embedded junction Schottky barrier diode (JBSD) having P-shield (PS) regions surrounding bottoms of source-body-Schottky contact (SBSC) trenches for gate oxide electric-field and switching loss reductions is disclosed. A source metal connects with the PS regions and the JBSD directly. Sidewall P (SP) regions are formed along a portion of sidewalls of the SBSC trenches to improve a tradeoff between a drain-source leakage current of the SiC trench MOSFET and a forward voltage of the JBSD. The device further comprises an N-type shield region formed below each of gate trenches for gate oxide electric field strength and specific on-resistance reductions.

## Claims

### Claim 1

A silicon carbide (SiC) power device comprising a plurality of unit cells with each unit cell in an active area comprising:
an epitaxial layer of a first conductivity type on a substrate;
a gate trench formed in said active area surrounded by a source region of said first conductivity type encompassed in a body region of a second conductivity type at a top portion of said epitaxial layer;
a source-body-Schottky contact (SBSC) trench penetrating through said source region and said body region and extending into said epitaxial layer;
a P-shield (PS) region of said second conductivity type for gate oxide electric-field reduction surrounding a bottom of said SBSC trench and being spaced apart from said gate trench;
a body contact region of said second conductivity type disposed in said body region;
a body combination area comprising said body region and body contact region;
a sidewall P (SP) region of said second conductivity type formed selectively along a portion of sidewalls of said SBSC trench, connecting said PS region to said body contact region;
a source metal filling into said SBSC trench to contact with said source region, said body contact region and said PS region; and form a Schottky barrier diode (SBD) region by making a Schottky contact with said epitaxial layer between said body contact region and said buried PS region;
a junction barrier Schottky diode (JBSD) region formed between said source region and a bottom of said PS region, comprising a first PN (P-type/N-type) junction diode, a second PN junction diode and said SBD, wherein said first PN junction diode formed between a body combination area and said epitaxial layer, and a second PN junction diode formed between said buried PS region and said epitaxial layer.

### Claim 2 (depends on 1)

The SiC power device of claim 1, wherein a gate electrode disposed in said gate trench surrounded with a first insulating film on a bottom of said gate trench, and with a gate oxide on sidewalls of said gate trench; said first insulating film having a thickness greater than said gate oxide.

### Claim 3 (depends on 2)

The SiC power device of claim 2, wherein said SBSC trench has a trench depth deeper than a trench depth of said gate trench.

### Claim 4 (depends on 1)

The SiC power device of claim 1, wherein a gate electrode and a shielded gate electrode disposed in said gate trench, said shielded gate electrode insulated from said epitaxial layer by a first insulating film, said gate electrode insulated from said epitaxial layer by a gate oxide, said shielded gate electrode and said gate electrode insulated from each other by an Inter-polysilicon Oxide (IPO) film, said gate oxide having a thickness less than a thickness of said first insulating film.

### Claim 5 (depends on 4)

The SiC power device of claim 4, wherein said shielded gate electrode is disposed in a lower portion and said gate electrode is disposed in an upper portion of said gate trench.

### Claim 6 (depends on 4)

The SiC power device of claim 4, wherein said shielded gate electrode is disposed in a middle and said gate electrode is a pair of split gate electrodes disposed surrounding an upper portion of said shielded gate electrode.

### Claim 7 (depends on 4)

The SiC power device of claim 4, wherein said substrate has said first conductivity type and said epitaxial layer has multiple stepped epitaxial (MSE) layers with different doping concentrations decreasing stepwise in a direction from said substrate to a top surface of said epitaxial layer, wherein each of said MSE layers has a uniform doping concentration as grown.

### Claim 8 (depends on 7)

The SiC power device of claim 7, wherein said epitaxial layer comprises at least two stepped epitaxial layers of different doping concentrations including a bottom epitaxial layer with a doping concentration D1 and a top epitaxial layer above said bottom epitaxial layer with a doping concentration D2, wherein said D2<said D1.

### Claim 9 (depends on 4)

The SiC power device of claim 4, wherein said epitaxial layer further comprising an oxide charge balance (OCB) region and a buffer region; said OCB region of said first conductivity type formed in a mesa area between two adjacent said gate trenches below said body regions and above a bottom of said shielded gate electrode; said buffer region of said first conductivity in said epitaxial layer formed between said substrate and said OCB region; and said epitaxial layer in said OCB region has MSE layers with different doping concentrations decreasing stepwise in a direction from a bottom of said shielded gate electrode to said body regions along sidewalls of said gate trench, wherein each of said MSE layers has a uniform doping concentration as grown; and said epitaxial layer in said buffer region has a doping concentration lower than doping concentrations of said MSE layers in said OCB region.

### Claim 10 (depends on 1)

The SiC power device of claim 1, wherein said SP region is formed along a first sidewall of said SBSC trench and said SBD is formed along a second sidewall opposite to said first sidewall of said SBSC trench.

### Claim 11 (depends on 1)

The SiC power device of claim 1, wherein said SP and SBD regions are alternately formed along two sidewalls of said SBSC trench.

### Claim 12 (depends on 1)

The SiC power device of claim 1, further comprising a current spreading region of said first conductivity type surrounding upper portions of sidewalls of said gate trench, wherein said current spreading layer has a doping concentration higher than a doping concentration of said epitaxial layer.

### Claim 13 (depends on 1)

The SiC power device of claim 1, further comprising at least one N-shield (NS) region of said first conductivity type disposed at a position deeper than said gate trench in said epitaxial layer with a doping concentration higher than a doping concentration of said epitaxial layer.

### Claim 14 (depends on 1)

The SiC power device of claim 1, further comprising a second PS region of said second conductivity type surrounding a sidewall of said gate trench on an opposite side of said JBSD region and adjoining said body region, and extending further along a portion of a bottom of said gate trench.

### Claim 15 (depends on 1)

The SiC power device of claim 1, wherein said substrate has said first conductivity type and epitaxial layer is a single epitaxial layer with a uniform doping concentration.

### Claim 16 (depends on 1)

The SiC power device of claim 1, wherein said substrate has said second conductivity type, further comprising a buffer layer of said first conductivity type with a resistivity Rb sandwiched between said substrate and said epitaxial layer having a uniform doping concentration with a resistivity R, wherein said R>said Rb.

### Claim 17 (depends on 1)

The SiC power device of claim 1, wherein said substrate has said second conductivity type, further comprising a buffer layer of said first conductivity type with a resistivity Rb sandwiched between said substrate and said epitaxial layer with a resistivity R, wherein said R>said Rb, and a plurality of heavily doped regions of said first conductivity type in said substrate to form a plurality of alternating P+ and N+ regions in said substrate.

### Claim 18 (depends on 1)

The SiC power device of claim 1, wherein said PS region has a doping concentration higher than a doping concentration of said SP region.

### Claim 19 (depends on 1)

The SiC device of claim 1, wherein said source metal has multiple metal films comprising a Nickel as a first metal film, a Titanium as a second metal film, an Aluminum as a third metal film and a Tungsten as a fourth metal film.

### Claim 20 (depends on 1)

The SiC device of claim 1, wherein said SBSC trench having a first type SBSC trench and a second type SBSC trench; said first type SBSC trench is formed above said second type SBSC trench and has a trench width wider than a trench width of said second type gate trench; said PS region surrounding sidewalls and a bottom of said second SBSC trench.