# US 12,604,503 B2 · Profile control of isolation structures in semiconductor devices

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- Number: US 12,604,503 B2
- Document ID: US12604503B2
- Status: Granted
- Kind: B2
- Application number: 18/168,968
- Filed: 2023-02-14
- Published: 2024-08-15
- Granted: 2026-04-14
- Earliest claimed: 2023-02-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tzu-Ging Lin
- Web page: https://patentgrep.com/patent/US12604503B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 50/242: {of Group IV materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured layers on first and second fin bases, forming cladding layers on sidewalls of the first and second nanostructured layers, forming a polysilicon structure on the first and second nanostructured layers, removing a portion of the polysilicon structure to form a first opening on the second nanostructured layers, removing a portion of the second nanostructured layers through the first opening to form a second opening on the second fin base, removing a portion of the second fin base through the second opening to form a third opening on the substrate, removing a portion of the substrate through the third opening to form a fourth opening in the substrate, and depositing an insulation material to fill the first, second, third, and fourth openings.

## Claims

### Claim 1

A method, comprising:
forming first and second fin bases on a substrate;
forming first and second nanostructured layers on the first and second fin bases, respectively;
forming cladding layers on sidewalls of the first and second nanostructured layers;
forming a polysilicon structure on the first and second nanostructured layers and the cladding layers;
removing a portion of the polysilicon structure to form a first opening on the second nanostructured layers;
removing a portion of the second nanostructured layers through the first opening to form a second opening on the second fin base;
removing a portion of the second fin base through the second opening to form a third opening on the substrate;
removing a portion of the substrate through the third opening to form a fourth opening in the substrate; and
depositing an insulation material to fill the first, second, third, and fourth openings.

### Claim 2 (depends on 1)

The method of claim 1, wherein removing the portion of the substrate through the third opening comprises performing an etch process in a plasma comprising halide ions and radicals with a halide ion-to-radical concentration ratio substantially equal to 1.

### Claim 3 (depends on 1)

The method of claim 1, wherein removing the portion of the substrate through the third opening comprises performing an etch process at a bias power greater than about 100 W and in a plasma comprising halide ions and radicals with a halide ion-to-radical concentration ratio greater than 1.

### Claim 4 (depends on 1)

The method of claim 1, wherein removing the portion of the substrate through the third opening comprises performing an etch process at a pressure greater than about 20 mTorr and in a plasma comprising halide ions and radicals with a halide ion-to-radical concentration ratio less than 1.

### Claim 5 (depends on 1)

The method of claim 1, wherein removing the portion of the substrate through the third opening comprises forming the fourth opening with curved sidewall profiles and bottom tip ends with obtuse angles.

### Claim 6 (depends on 1)

The method of claim 1, wherein removing the portion of the substrate through the third opening comprises forming the fourth opening with tapered sidewall profiles and substantially planar bottom profiles.

### Claim 7 (depends on 1)

The method of claim 1, further comprising removing portions of the cladding layers on the sidewalls of the second nanostructured layers during the removing of the portion of the second nanostructured layers through the first opening.

### Claim 8 (depends on 1)

The method of claim 1, wherein removing the portion of the polysilicon structure comprises forming the first opening wider than the second opening.

### Claim 9 (depends on 1)

The method of claim 1, wherein removing the portion of the second nanostructured layers comprises forming the second opening wider than the third opening.

### Claim 10 (depends on 1)

The method of claim 1, wherein removing the portion of the substrate through the third opening comprises forming the fourth opening wider than the third opening.

### Claim 11

A method, comprising:
forming first and second fin bases on a substrate;
forming first and second nanostructured layers on the first and second fin bases, respectively;
forming a first isolation structure between the first and second fin bases;
forming a second isolation structure on the first isolation structure and between the first and second nanostructured layers;
forming a polysilicon structure on the first and second nanostructured layers; and
forming a third isolation structure, comprising:
forming first and second isolation portions of the third isolation structure in the substrate;
forming third and fourth isolation portions of the third isolation structure on opposite sides of the first isolation structure;
forming fifth and sixth isolation portions of the third isolation structure on opposite sides of the second isolation structure; and
forming a seventh isolation portion of the third isolation structure in the polysilicon structure.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming the first and second isolation portions comprises etching portions of the substrate with a plasma comprising bromide ions and radicals with a bromide ion-to-radical concentration ratio substantially equal to 1.

### Claim 13 (depends on 11)

The method of claim 11, wherein forming the first and second isolation portions comprises etching portions of the substrate at a bias power greater than about 100 W and in a plasma comprising bromide ions and radicals with a bromide ion-to-radical concentration ratio greater than 1.

### Claim 14 (depends on 11)

The method of claim 11, wherein forming the first and second isolation portions comprises etching portions of the substrate at a pressure greater than about 20 mTorr and in a plasma comprising bromide ions and radicals with a bromide ion-to-radical concentration ratio less than 1.

### Claim 15 (depends on 11)

The method of claim 11, wherein forming the first and second isolation portions comprises etching portions of the substrate to form first and second openings with curved sidewall profiles and bottom tip ends with obtuse angles.

### Claim 16 (depends on 11)

The method of claim 11, wherein forming the first and second isolation portions comprises etching portions of the substrate to form first and second openings with tapered sidewall profiles and substantially planar bottom profiles.

### Claim 17

A semiconductor device, comprising:
a substrate;
first and second fin bases disposed on the substrate;
first and second nanostructured layers disposed on the first and second fin bases, respectively;
first and second gate structures surrounding the first and second nanostructured layers, respectively;
first and second shallow trench isolation (STI) regions disposed on opposite sides of the first and second fin bases;
first and second isolation structures disposed on the first and second STI regions, respectively; and
a third isolation structure, comprising:
a first isolation portion disposed between the first and second gate structures;
a second isolation portion disposed between and in contact with the first and second isolation structures;
a third isolation portion disposed between and in contact with the first and second STI regions; and
a fourth isolation portion disposed in the substrate, wherein the first isolation portion is wider than the second and third isolation portions.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the fourth isolation portion overlaps bottom surfaces of the first and second STI regions.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the fourth isolation portion comprises curved sidewall profiles and bottom tip ends with obtuse angles.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, wherein the fourth isolation portion comprises tapered sidewall profiles and substantially planar bottom profiles.