Nanochannel gallium nitride-based device and manufacturing method thereof

A nanochannel gallium nitride (GaN)-based device, comprising:

• a substrate layer (1), a nucleation layer (2), a buffer layer (3), a channel region (4), an insertion layer (5), a barrier layer (6), a cap layer (7), a first n+-doped material layer (8), a second n+-doped material layer (9), a source electrode (10), a drain electrode (11), and a gate electrode (12);
• wherein the substrate layer (1), the nucleation layer (2), the buffer layer (3), the channel region (4), the insertion layer (5), the barrier layer (6) and the cap layer (7) are sequentially stacked in that order;
• wherein the first n+-doped material layer (8) is disposed in a source electrode region, and penetrates through the cap layer (7), the barrier layer (6), and the insertion layer (5), a bottom of the first n+-doped material layer (8) is disposed under channels of the channel region (4), the first n+-doped material layer (8) comprises a first arrayed pattern edge (81) facing towards the drain electrode (11), and the source electrode (10) is disposed on the first n+-doped material layer (8);
• wherein the second n+-doped material layer (9) is disposed in a drain electrode region and penetrates through the cap layer (7), the barrier layer (6), and the insertion layer (5), a bottom of the second n+-doped material layer (9) is disposed under the channels of the channel region (4), the second n+-doped material layer (9) comprises a second arrayed pattern edge (91) facing towards the source electrode (10), and the drain electrode (11) is disposed on the second n+-doped material layer (9);
• wherein a part of the channel region (4), the insertion layer (5), the barrier layer (6) and the cap layer (7) together form an arrayed nanochannel structure (71) between the source electrode region and the drain electrode region, the first arrayed pattern edge (81) is interdigitated with an end of the arrayed nanochannel structure (71), and the second arrayed pattern edge (91) is interdigitated with another end of the arrayed nanochannel structure (71);
• and
• wherein the gate electrode (12) is disposed between the first n+-doped material layer (8) and the second n+-doped material layer (9), on the arrayed nanochannel structure (71) and in recesses (72) defined by the arrayed nanochannel structure (71), to form a three-dimensional gate-all-around structure.