# US 12,604,501 B2 · Semiconductor device

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- Number: US 12,604,501 B2
- Document ID: US12604501B2
- Status: Granted
- Kind: B2
- Application number: 17/672,233
- Filed: 2022-02-15
- Published: 2023-01-12
- Granted: 2026-04-14
- Earliest claimed: 2021-07-06
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dong Woo Kim; Gyeom Kim; Jin Bum Kim; Dong Suk Shin; Sang Moon Lee
- Web page: https://patentgrep.com/patent/US12604501B2

## CPC

- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/0112: {using conductive layers comprising silicides}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device comprises an active pattern on a substrate; a plurality of nanosheets spaced apart from each other; a gate electrode surrounding each of the nanosheets; a field insulating layer surrounding side walls of the active pattern; an interlayer insulating layer on the field insulating layer; a source/drain region comprising a first doping layer on the active pattern, a second doping layer on the first doping layer, and a capping layer forming side walls adjacent to the interlayer insulating layer; a source/drain contact electrically connected to, and on, the source/drain region, and a silicide layer between the source/drain region and the source/drain contact which contacts contact with the second doping layer and extends to an upper surface of the source/drain region. The capping layer extends from an upper surface of the field insulating layer to the upper surface of the source/drain region along side walls of the silicide layer.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
an active pattern which extends in a first horizontal direction on the substrate;
a plurality of nanosheets spaced apart from each other in a vertical direction and extending in the first horizontal direction on the active pattern;
a gate electrode which extends in a second horizontal direction different from the first horizontal direction on the substrate and surrounds each of the plurality of nanosheets;
a field insulating layer on the substrate which surrounds side walls of the active pattern;
an interlayer insulating layer on the field insulating layer;
a source/drain region on at least one side of the gate electrode on the active pattern which comprises a first doping layer on the active pattern, a second doping layer on the first doping layer, and a capping layer that comprises side walls adjacent to the interlayer insulating layer;
a source/drain contact which is electrically connected to the source/drain region and is on the source/drain region; and
a silicide layer between the source/drain region and the source/drain contact wherein the silicide layer is in contact with the second doping layer and extends to an upper surface of the source/drain region on the second doping layer,
wherein the capping layer extends from an upper surface of the field insulating layer to the upper surface of the source/drain region along side walls of the silicide layer,
wherein the first doping layer overlaps the second doping layer in the first horizontal direction and the second horizontal direction, and
wherein the first doping layer overlaps the source/drain contact in the first horizontal direction.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein:
the first doping layer comprises silicon which is doped with a first impurity at a first concentration;
the second doping layer comprises silicon doped with the first impurity at a second concentration higher than the first concentration or silicon carbide doped with a second impurity; and
the capping layer comprises silicon which is not doped with an impurity.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first impurity is phosphorus (P), and the second impurity comprises any one or more of phosphorus (P), arsenic (As), and antimony (Sb).

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein an uppermost surface of the silicide layer is coplanar with an uppermost surface of the capping layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein:
the silicide layer is between the second doping layer and a contact barrier layer of the source/drain contact and is further between the capping layer and the contact barrier layer, and wherein the silicide layer further comprises:
a first layer along a surface of the second doping layer;
a second layer along side walls of the capping layer; and
a third layer between the first layer and the contact barrier layer of the source/drain contact, and between the second layer and the contact barrier layer of the source/drain contact.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein at least one of the first to third layers comprises at least one different material from one or more of the other layers.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the silicide layer is in contact with the capping layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein:
the second doping layer is between the silicide layer and the capping layer, and
the second doping layer extends along side walls of the capping layer to the upper surface of the source/drain region.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the silicide layer comprises:
a first layer along at least a portion of a surface of the second doping layer; and
a second layer between the first layer and the source/drain contact.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the silicide layer comprises a single film between the second doping layer and the source/drain contact.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the plurality of nanosheets comprises first, second, and third nanosheets, and wherein in a cross section which is cut in the first horizontal direction along a center line that equally divides the active pattern in the second horizontal direction, a bottom surface of the second doping layer is between the active pattern and the first nanosheet.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the plurality of nanosheets comprises first, second, and third nanosheets, and wherein in a cross section which is cut in the first horizontal direction along a center line that equally divides the active pattern in the second horizontal direction, a bottom surface of the second doping layer is between the second nanosheet and the third nanosheet of the plurality of nanosheets.

### Claim 13

A semiconductor device comprising:
a substrate;
an active pattern which extends in a first horizontal direction on the substrate;
a plurality of nanosheets spaced apart from each other in a vertical direction and extending in the first horizontal direction on the active pattern;
a gate electrode which extends in a second horizontal direction different from the first horizontal direction on the substrate and surrounds each of the plurality of nanosheets;
a field insulating layer on the substrate which surrounds side walls of the active pattern;
an interlayer insulating layer on the field insulating layer;
a source/drain region on at least one side of the gate electrode on the active pattern which comprises a capping layer that comprises side walls adjacent to the interlayer insulating layer;
a source/drain contact which is electrically connected to the source/drain region and is on the source/drain region; and
a silicide layer between the source/drain region and the source/drain contact wherein the silicide layer comprises a first layer along an inner surface of the source/drain region and a second layer disposed between the first layer and the source/drain contact which extends along side walls of the capping layer to an upper surface of the source/drain region,
wherein:
the first layer and the second layer comprise different materials from each other,
the capping layer comprises silicon that is not doped with an impurity, and
an uppermost surface of the silicide layer is coplanar with an uppermost surface of the capping layer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the source/drain region further comprises:
a first doping layer on the active pattern which comprises silicon doped with a first impurity at a first concentration; and
a second doping layer on the first doping layer which comprises silicon doped with the first impurity at a second concentration higher than the first concentration or silicon carbide doped with a second impurity.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein:
the second doping layer is between the silicide layer and the capping layer, and
the second doping layer extends along the side walls of the capping layer to the upper surface of the source/drain region.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, wherein the capping layer extends from an upper surface of the field insulating layer to the upper surface of the source/drain region along side walls of the silicide layer.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, wherein the silicide layer further comprises a third layer between the second layer and the capping layer which is in contact with the capping layer and extends along the side walls of the capping layer to the upper surface of the source/drain region.

### Claim 18

A semiconductor device comprising:
a substrate having a first region and a second region;
a first active pattern which extends in a first horizontal direction on the first region of the substrate;
a first plurality of nanosheets spaced apart from each other in a vertical direction and extending in the first horizontal direction on the first active pattern;
a first gate electrode which extends in a second horizontal direction different from the first horizontal direction on the first region of the substrate and surrounds each of the plurality of nanosheets;
a field insulating layer on the substrate which surrounds side walls of the first active pattern;
an interlayer insulating layer on the field insulating layer;
a first source/drain region on at least one side of the first gate electrode on the first active pattern which comprises a first doping layer on the first active pattern, a second doping layer on the first doping layer, and a first capping layer that comprises side walls adjacent to the interlayer insulating layer;
a first source/drain contact which is electrically connected to the first source/drain region and is on the first source/drain region; and
a first silicide layer between the first source/drain region and the first source/drain contact wherein the first silicide layer comprises a first layer along a surface of the second doping layer, a second layer extending to an upper surface of the first source/drain region along side walls of the first capping layer, and a third layer between the first layer and the first source/drain contact and between the second layer and the first source/drain contact,
wherein one or more of the first layer, the second layer and the third layer comprise at least one different material from one or more of the other layers,
the first capping layer comprises silicon that is not doped with an impurity, and
the first capping layer extends from an upper surface of the field insulating layer to the upper surface of the first source/drain region along side walls of the first silicide layer.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the first plurality of nanosheets comprises first, second, and third nanosheets, the semiconductor device further comprising:
a second active pattern extending in the first horizontal direction on the second region of the substrate;
a second plurality of nanosheets comprising fourth to sixth nanosheets spaced apart from each other in the vertical direction and extending in the first horizontal direction on the second active pattern;
a second gate electrode which extends in the second horizontal direction on the second region of the substrate and surrounds each of the fourth to sixth nanosheets;
a second source/drain region on at least one side of the second gate electrode on the second active pattern wherein the second source/drain region comprises a third doping layer on the second active pattern, a fourth doping layer on the third doping layer, and a second capping layer that comprises side walls adjacent to the interlayer insulating layer;
a second source/drain contact which is electrically connected to the second source/drain region and is on the second source/drain region; and
a second silicide layer between the second source/drain region and the second source/drain contact which comprises a fourth layer along a surface of the fourth doping layer, a fifth layer extending to an upper surface of the second source/drain region along side walls of the second capping layer, and a sixth layer between the fourth layer and the second source/drain contact and between the fifth layer and the second source/drain contact,
wherein one or more of the fourth layer, the fifth layer and the sixth layer comprise at least one different material from one or more of the fourth layer, fifth layer, and sixth layer,
the second capping layer comprises silicon that is not doped with an impurity,
the second capping layer extends from the upper surface of the field insulating layer to the upper surface of the second source/drain region along side walls of the second silicide layer,
wherein in a cross section that is cut in the first horizontal direction along a first center line that equally divides the first active pattern in the second horizontal direction, a bottom surface of the second doping layer is between the first active pattern and the first nanosheet, and
in a cross section that is cut in the first horizontal direction along a second center line that equally divides the second active pattern in the second horizontal direction, a bottom surface of the fourth doping layer is between the fifth nanosheet and the sixth nanosheet.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein the first doping layer comprises silicon which is doped with a first impurity at a first concentration,
the second doping layer comprises silicon doped with the first impurity at a second concentration higher than the first concentration or silicon carbide doped with a second impurity, and
the first capping layer comprises silicon that is not doped with an impurity.