# US 12,604,499 B2 · Semiconductor devices with embedded ferroelectric field effect transistors

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- Number: US 12,604,499 B2
- Document ID: US12604499B2
- Status: Granted
- Kind: B2
- Application number: 18/359,323
- Filed: 2023-07-26
- Published: 2024-01-18
- Granted: 2026-04-14
- Earliest claimed: 2020-02-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chia-Hao Chang; Lin-Yu Huang; Han-Jong Chia; Bo-Feng Young; Yu-Ming Lin
- Web page: https://patentgrep.com/patent/US12604499B2

## CPC

- H10B 53/30: characterised by the memory core region
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/689: {having ferroelectric layers}
- H10D 84/834: {comprising FinFETs}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A device includes a substrate, gate stacks, source/drain (S/D) features over the substrate, S/D contacts over the S/D features, and one or more dielectric layers over the gate stacks and the S/D contacts. A via structure penetrates the one or more dielectric layers and electrically contacts one of the gate stacks and the S/D contacts. And a ferroelectric (FE) stack is over the via structure and directly contacting the via structure, wherein the FE stack includes an FE feature and a top electrode over the FE feature.

## Claims

### Claim 1

A device, comprising:
a substrate;
gate stacks and source/drain (S/D) features over the substrate;
S/D contacts over the S/D features;
S/D dielectric caps over the S/D contacts;
an S/D via penetrating one of the S/D dielectric caps and electrically contacting one of the S/D contacts, wherein the S/D via is above the one of the S/D contacts; and
a ferroelectric (FE) stack over the S/D via and directly contacting the S/D via, wherein the FE stack includes an FE feature and a top electrode over the FE feature.

### Claim 2 (depends on 1)

The device of claim 1, further comprising:
a dielectric layer over the FE stack; and
conductive features embedded in the dielectric layer and electrically connected to the FE stack,
wherein the S/D via includes a first metal, the conductive features include a second metal, and the first metal has a higher melting point than the second metal.

### Claim 3 (depends on 2)

The device of claim 2, wherein the conductive features include copper, and the S/D via is free of copper.

### Claim 4 (depends on 1)

The device of claim 1, further comprising:
one or more dielectric layers between the FE stack and the S/D dielectric caps, and the S/D via penetrates through the one or more dielectric layers to electrically connect the FE stack to the one of the S/D contacts.

### Claim 5 (depends on 1)

The device of claim 1, further comprising:
a via glue layer between the S/D via and the one of the S/D dielectric caps.

### Claim 6 (depends on 1)

The device of claim 1, wherein the FE feature directly contacts the S/D via.

### Claim 7 (depends on 1)

The device of claim 1, wherein the FE stack further includes a bottom electrode under the FE feature, and the bottom electrode directly contacts the S/D via.

### Claim 8 (depends on 1)

The device of claim 1, further comprising dielectric liners on sidewalls of the FE stack.

### Claim 9

A device, comprising:
a substrate;
gate stacks and source/drain (S/D) features over the substrate;
S/D contacts over the S/D features;
an S/D via landing on one of the S/D contacts, wherein the S/D via is above the one of the S/D contacts;
a ferroelectric (FE) stack landing on the S/D via, wherein the FE stack includes an FE feature and a top electrode over the FE feature; and
an S/D metal line over and electrically connected to the FE stack.

### Claim 10 (depends on 9)

The device of claim 9,
wherein the S/D via includes Co, W, Ru, Mo, or combinations thereof,
wherein the S/D metal line includes copper or aluminum.

### Claim 11 (depends on 9)

The device of claim 9, further comprising:
a dielectric layer directly over the gate stacks and the S/D contacts, wherein the S/D via penetrates through the dielectric layer to land on the one of the S/D contacts.

### Claim 12 (depends on 11)

The device of claim 11, further comprising:
an S/D dielectric cap directly over the S/D features and directly below the dielectric layer, wherein the S/D via penetrates through the S/D dielectric cap to land on the one of the S/D contacts.

### Claim 13 (depends on 9)

The device of claim 9, further comprising:
gate dielectric caps directly over the gate stacks;
a gate via penetrating through one of the gate dielectric caps to land on one of the gate stacks, wherein the gate via is above the one of the gate stacks; and
a second FE stack landing on the gate via, wherein the second FE stack includes an FE feature and a top electrode over the FE feature.

### Claim 14 (depends on 13)

The device of claim 13, further comprising:
a gate metal line over and electrically connected to the second FE stack,
wherein the gate via includes Co, W, Ru, Mo, or combinations thereof,
wherein the gate metal line includes copper or aluminum.

### Claim 15

A device, comprising:
a substrate;
gate stacks and source/drain (S/D) features over the substrate;
a gate via landing on one of the gate stacks, wherein the gate via is above the one of the gate stacks, wherein the gate via penetrates through one or more dielectric layers to land on the one of the gate stacks;
a ferroelectric (FE) stack landing on the gate via, wherein the FE stack includes an FE feature and a top electrode over the FE feature; and
a gate metal line over and electrically connected to the FE stack.

### Claim 16 (depends on 15)

The device of claim 15,
wherein the gate via includes Co, W, Ru, Mo, or combinations thereof,
wherein the gate metal line includes copper or aluminum.

### Claim 17 (depends on 15)

The device of claim 15, wherein the one or more dielectric layers include a dielectric layer directly above the gate stacks and the S/D features, wherein the gate via penetrates through the dielectric layer to land on the one of the gate stacks.

### Claim 18 (depends on 17)

The device of claim 17, further comprising:
a gate dielectric cap directly over the one of the gate stacks and directly below the dielectric layer, wherein the gate via penetrates through the gate dielectric cap to land on the one of the gate stacks.

### Claim 19 (depends on 15)

The device of claim 15, further comprising:
S/D contacts over the S/D features;
an S/D via landing on one of the S/D contacts, wherein the S/D via is above the one of the S/D contacts; and
a second ferroelectric (FE) stack landing on the S/D via, wherein the second FE stack includes an FE feature and a top electrode over the FE feature.

### Claim 20 (depends on 19)

The device of claim 19, further comprising:
an S/D metal line over and electrically connected to the second FE stack,
wherein the S/D via includes Co, W, Ru, Mo, or combinations thereof,
wherein the S/D metal line includes copper or aluminum.