# US 12,604,498 B2 · Memory device

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- Number: US 12,604,498 B2
- Document ID: US12604498B2
- Status: Granted
- Kind: B2
- Application number: 18/624,513
- Filed: 2024-04-02
- Published: 2024-07-25
- Granted: 2026-04-14
- Earliest claimed: 2018-08-09
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Tatsuya Onuki; Kiyoshi Kato; Tomoaki Atsumi; Shunpei Yamazaki
- Web page: https://patentgrep.com/patent/US12604498B2

## CPC

- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/05: {Making the transistor}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/674: {characterised by the active materials}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.

## Claims

### Claim 1

A memory device comprising a cell array, the cell array comprising:
a first sub cell array including a first memory cell and a second memory cell; and
a second sub cell array including a third memory cell,
wherein the first memory cell includes a first transistor, the second memory cell includes a second transistor, and the third memory cell includes a third transistor,
wherein the second transistor is closest to the first transistor among the other transistors in the first sub cell array, and the third transistor is closest to the second transistor among the other transistors in the second sub cell array,
wherein a shortest distance between a gate electrode of the second transistor and a gate electrode of the third transistor is larger than a shortest distance between a gate electrode of the first transistor and the gate electrode of the second transistor,
wherein the first transistor, the second transistor, and the third transistor are connected to a same word line, and
wherein the shortest distance between the gate electrode of the second transistor and the gate electrode of the third transistor is 3.5 μm or less.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein each of the first transistor, the second transistor, and the third transistor includes a first oxide layer, a second oxide layer over the first oxide layer, a source electrode and a drain electrode over the second oxide layer, a third oxide layer between the source electrode and the drain electrode, a first insulating layer over the third oxide layer, and a first conductive layer over the first insulating layer.

### Claim 3 (depends on 2)

The memory device according to claim 2, further comprising a second conductive layer below the first oxide layer.

### Claim 4 (depends on 1)

The memory device according to claim 1, wherein a retention potential of each of the first memory cell, the second memory cell, and the third memory cell is 0.6 V or higher.

### Claim 5 (depends on 1)

The memory device according to claim 1, wherein the shortest distance between the gate electrode of the first transistor and the gate electrode of the second transistor is 2.5 μm or less.

### Claim 6

A memory device comprising a cell array, the cell array comprising:
a first sub cell array including a first memory cell and a second memory cell;
a second sub cell array including a third memory cell; and
a dummy memory cell provided between the second memory cell and the third memory cell,
wherein the first memory cell includes a first transistor, the second memory cell includes a second transistor, and the third memory cell includes a third transistor,
wherein the second transistor is closest to the first transistor among the other transistors in the first sub cell array, and the third transistor is closest to the second transistor among the other transistors in the second sub cell array,
wherein a shortest distance between a gate electrode of the second transistor and a gate electrode of the third transistor is larger than a shortest distance between a gate electrode of the first transistor and the gate electrode of the second transistor,
wherein the first transistor, the second transistor, and the third transistor are connected to a same word line, and
wherein the shortest distance between the gate electrode of the second transistor and the gate electrode of the third transistor is 3.5 μm or less.

### Claim 7 (depends on 6)

The memory device according to claim 6, wherein each of the first transistor, the second transistor, and the third transistor includes a first oxide layer, a second oxide layer over the first oxide layer, a source electrode and a drain electrode over the second oxide layer, a third oxide layer between the source electrode and the drain electrode, a first insulating layer over the third oxide layer, and a first conductive layer over the first insulating layer.

### Claim 8 (depends on 7)

The memory device according to claim 7, further comprising a second conductive layer below the first oxide layer.

### Claim 9 (depends on 6)

The memory device according to claim 6, wherein a retention potential of each of the first memory cell, the second memory cell, and the third memory cell is 0.6 V or higher.

### Claim 10 (depends on 6)

The memory device according to claim 6, wherein the shortest distance between the gate electrode of the first transistor and the gate electrode of the second transistor is 2.5 μm or less.