# US 12,604,496 B2 · Epitaxy everywhere based self-aligned direct backside contact

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- Number: US 12,604,496 B2
- Document ID: US12604496B2
- Status: Granted
- Kind: B2
- Application number: 17/950,316
- Filed: 2022-09-22
- Published: 2024-03-28
- Granted: 2026-04-14
- Earliest claimed: 2022-09-22
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ruilong Xie; Kisik Choi; Muthumanickam Sankarapandian; Shogo Mochizuki
- Web page: https://patentgrep.com/patent/US12604496B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/0198: {forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Self-aligned direct backside contacts by an epitaxy everywhere under source/drain region approach are provided. In one aspect, a semiconductor device includes: a field-effect transistor(s) on a backside interlayer dielectric; an epitaxial contact placeholder in the backside interlayer dielectric that directly contacts a first source/drain region of the field-effect transistor(s); and a self-aligned direct backside contact in the backside interlayer dielectric that directly contacts a second source/drain region of the field-effect transistor(s). The epitaxial contact placeholder extends a distance d1 into the backside interlayer dielectric from the first source/drain region, and the self-aligned direct backside contact extends a distance d2 into the backside interlayer dielectric from the second source/drain region, where d2>d1. The field-effect transistor(s) can include a stack of active layers surrounded by a gate, and the first/second source/drain regions on opposite sides thereof. A method of fabricating the present semiconductor device is also provided.

## Claims

### Claim 1

A semiconductor device, comprising:
at least one field-effect transistor on a backside interlayer dielectric;
an epitaxial contact placeholder embedded in, and surrounded by, the backside interlayer dielectric, wherein the epitaxial contact placeholder directly contacts a first source/drain region of the at least one field-effect transistor; and
a self-aligned direct backside contact embedded in, and surrounded by, the backside interlayer dielectric, wherein the self-aligned direct backside contact directly contacts a second source/drain region of the at least one field-effect transistor,
wherein the epitaxial contact placeholder extends a distance d1 into the backside interlayer dielectric from the first source/drain region, wherein the self-aligned direct backside contact extends a distance d2 into the backside interlayer dielectric from the second source/drain region, and wherein d2>d1.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a middle of line source/drain contact in direct contact with an end of the first source/drain region opposite the epitaxial contact placeholder.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the epitaxial contact placeholder comprises a material selected from the group consisting of: epitaxial silicon germanium (SiGe), an epitaxial III-V material, and combinations thereof.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the epitaxial contact placeholder comprises epitaxial SiGe.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the epitaxial SiGe comprises from about 15% germanium (Ge) to about 60% Ge.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a backside power rail disposed on the backside interlayer dielectric, wherein the backside power rail directly contacts the self-aligned direct backside contact.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the backside interlayer dielectric separates the epitaxial contact placeholder from the backside power rail.

### Claim 8

A semiconductor device, comprising:
at least one field-effect transistor on a backside interlayer dielectric, wherein the at least one field-effect transistor comprises a stack of active layers, a gate surrounding the active layers in a gate-all-around configuration, and source/drain regions on opposite sides of the stack of active layers;
an epitaxial contact placeholder embedded in, and surrounded by, the backside interlayer dielectric, wherein the epitaxial contact placeholder directly contacts a first one of the source/drain regions; and
a self-aligned direct backside contact embedded in, and surrounded by, the backside interlayer dielectric, wherein the self-aligned direct backside contact directly contacts a second one of the source/drain regions,
wherein the epitaxial contact placeholder extends a distance d1 into the backside interlayer dielectric from the first one of the source/drain regions, wherein the self-aligned direct backside contact extends a distance d2 into the backside interlayer dielectric from the second one of the source/drain regions, and wherein d2>d1.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising:
a middle of line source/drain contact in direct contact with an end of the first one of the source/drain regions opposite the epitaxial contact placeholder.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the epitaxial contact placeholder comprises epitaxial SiGe.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the epitaxial SiGe comprises from about 15% Ge to about 60% Ge.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, further comprising:
a backside power rail disposed on the backside interlayer dielectric, wherein the backside power rail directly contacts the self-aligned direct backside contact.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the backside interlayer dielectric separates the epitaxial contact placeholder from the backside power rail.