# US 12,604,494 B2 · Gate end cap and boundary placement in transistor structures for N-metal oxide semiconductor (N-MOS) performance tuning

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- Number: US 12,604,494 B2
- Document ID: US12604494B2
- Status: Granted
- Kind: B2
- Application number: 17/470,993
- Filed: 2021-09-09
- Published: 2023-03-09
- Granted: 2026-04-14
- Earliest claimed: 2021-09-09
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Andrew Smith; Brian Greene; Seonghyun Paik; Omair Saadat; Chung-Hsun Lin; Tahir Ghani
- Web page: https://patentgrep.com/patent/US12604494B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 30/0194: {the stacked channels having different properties}
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A transistor structure includes a channel region including first sidewall. A gate electrode includes a first layer having a first portion adjacent to the first sidewall and a second portion adjacent to a gate electrode boundary sidewall. The gate electrode includes a second layer between the first and second portions of the first layer. The first layer has a first composition associated with a first work function material, and has a first lateral thickness from the first sidewall. The second layer has a second composition associated with a second work function material. Depending one a second lateral thickness of the second layer, the second layer may modulate a threshold voltage (VT) of the transistor structure by more or less. In some embodiments, a ratio of the second lateral thickness to the first lateral thickness is less than three.

## Claims

### Claim 1

A device structure comprising:
a first plurality of channel regions in a stack of a first transistor, each of the channel regions comprising a first sidewall and a second sidewall opposite of the first sidewall;
a source region and a drain region coupled to opposite ends of the first plurality of channel regions; and
a gate electrode between the source regions and the drain regions, the gate electrode comprising:
a first layer comprising a first portion adjacent to the first sidewall and a second portion adjacent to a boundary sidewall spaced apart from the first sidewall, wherein the boundary sidewall comprises a dielectric material, and is a first distance away from a first gate dielectric layer that is adjacent to the first sidewall; and
a second layer directly adjacent to the first layer, and occupying a space between the first and second portions of the first layer;
wherein:
the first layer is a first workfunction material having a first composition associated with a first workfunction, wherein the first layer comprises a third portion below the second layer, wherein the third portion is contiguous with the first and second portions;
the first portion of the first layer is of a first lateral thickness from the first sidewall;
the second portion of the first layer is directly adjacent to a second gate electrode of a second transistor further comprising a second gate dielectric layer and a second plurality of channel regions in a stack;
the second layer is a second workfunction material having a second composition associated with a second workfunction, and is of a second lateral thickness from the first sidewall;
a ratio of the second lateral thickness to the first lateral thickness is less than three;
the first sidewalls of the first plurality of channel regions are laterally spaced apart by a distance from first sidewalls of the second plurality of channel regions; and
the second gate electrode is of a fourth lateral thickness equal to a difference between the distance minus a sum of the first lateral thickness, the second lateral thickness, a third lateral thickness of the second portion of the first layer, a lateral thickness of the first gate dielectric layer, and a lateral thickness of the second gate dielectric layer.

### Claim 2 (depends on 1)

The device structure of claim 1, wherein the third lateral thickness is substantially equal to the first lateral thickness, and wherein the first lateral thickness and the second lateral thickness each have a minimum value of 2 nm.

### Claim 3 (depends on 1)

The device structure of claim 1, wherein the second transistor comprises
a second source and a second drain coupled to ends of the second plurality of channel regions, and wherein the second gate electrode comprises a third workfunction material.

### Claim 4 (depends on 3)

The device structure of claim 3, wherein the ratio of the second lateral thickness to the first lateral thickness is greater than 0 and less than 2.5.

### Claim 5 (depends on 3)

The device structure of claim 3, wherein the first gate dielectric layer and second gate dielectric layer include a same material, and the third workfunction material has the same composition as the second workfunction material.

### Claim 6 (depends on 1)

The device structure of claim 1, wherein the first layer is around each of the plurality of channel regions, wherein a second portion of the second layer is adjacent to second sidewalls of the channel regions, opposite the first sidewalls, and has a lateral thickness that is greater than the first lateral thickness by more than the ratio of the second lateral thickness to the first lateral thickness.

### Claim 7 (depends on 1)

The device structure of claim 1, wherein the device structure further comprises a third transistor, the third transistor comprising a third gate electrode comprising:
a third layer comprising the first material associated with a first work function; and
a fourth layer directly adjacent to the third layer, the fourth layer comprising the second workfunction material;
wherein the third layer is adjacent to first channel sidewalls of the third transistor, and wherein a ratio of a lateral thickness of the fourth layer to the first lateral thickness is greater than the ratio of a lateral thickness of the third layer to the first lateral thickness.

### Claim 8 (depends on 7)

The device structure of claim 7, wherein a threshold voltage of the third transistor is at least 30% higher than a threshold voltage of the first transistor.

### Claim 9 (depends on 1)

A system comprising:
a battery;
an antenna; and
a processor coupled to the antenna, wherein the processor includes the device structure of claim 1.