# US 12,604,489 B2 · Semiconductor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,489 B2 - Document ID: US12604489B2 - Status: Granted - Kind: B2 - Application number: 18/221,495 - Filed: 2023-07-13 - Published: 2024-01-18 - Granted: 2026-04-14 - Earliest claimed: 2022-07-15 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Junrak Choi; Yaejin Hong; Jinsu Lee; Hongsik Chae - Web page: https://patentgrep.com/patent/US12604489B2 ## CPC - H10D 1/696: {comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688)} - H10B 12/033: {the capacitor extending over the transistor} - H10B 12/315: {with the capacitor higher than a bit line} - H10B 12/482: {Bit lines} - H10B 12/485: {Bit line contacts} - H10D 1/716: {having vertical extensions} - H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device includes a substrate, lower electrodes on the substrate, a dielectric layer covering the lower electrodes, and an upper electrode covering the dielectric layer. Each of the lower electrodes includes a first electrode layer having a cylindrical shape, a first insertion layer disposed on the first electrode layer and having a cylindrical shape, a second electrode layer disposed on the first insertion layer and extending to cover an upper end of the first electrode layer and an upper end of the first insertion layer. At least one of the first electrode layer and the second electrode layer has a first stress, and the first insertion layer has a second stress, different from the first stress. The first stress is one of tensile stress and compressive stress, and the second stress is the other of the tensile stress and the compressive stress. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate; a plurality of lower electrodes on the substrate; a dielectric layer covering the plurality of lower electrodes; and an upper electrode covering the dielectric layer, wherein each of the plurality of lower electrodes includes: a first electrode layer having a cylindrical shape, a first insertion layer on the first electrode layer and having a cylindrical shape, and a second electrode layer on the first insertion layer and extending to cover an upper end of the first electrode layer and an upper end of the first insertion layer, wherein at least one of the first electrode layer and the second electrode layer has a first stress, wherein the first insertion layer has a second stress different from the first stress, wherein the first stress is one of a tensile stress and a compressive stress, and wherein the second stress is the other of the tensile stress and the compressive stress. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first insertion layer is surrounded by the first electrode layer and the second electrode layer. ### Claim 3 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first stress is the tensile stress, and the second stress is the compressive stress. ### Claim 4 (depends on 1) The semiconductor device as claimed in claim 1, wherein: each of the first electrode layer and the second electrode layer includes at least one of polycrystalline silicon (Si), TiN, NbN, WN, VN, MoN, TaN, TiSiN, and TiCN, and the first insertion layer includes at least one of TiO, NbO, MoO, TaO, and TiON. ### Claim 5 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first insertion layer has a thickness greater than 0 angstroms and less than about 10 angstroms. ### Claim 6 (depends on 1) The semiconductor device as claimed in claim 1, wherein the upper end of the first electrode layer and the upper end of the first insertion layer are at a substantially same level. ### Claim 7 (depends on 1) The semiconductor device as claimed in claim 1, wherein an external side surface of the second electrode layer includes a portion vertically aligned with an external side surface of the first electrode layer. ### Claim 8 (depends on 1) The semiconductor device as claimed in claim 1, wherein the second electrode layer includes: a first pillar portion filling an internal space defined by the first insertion layer; and a second pillar portion on the first pillar portion and covering the upper end of the first electrode layer and the upper end of the first insertion layer. ### Claim 9 (depends on 8) The semiconductor device as claimed in claim 8, wherein: the first pillar portion has a first width, and the second pillar portion has a second width greater than the first width. ### Claim 10 (depends on 1) The semiconductor device as claimed in claim 1, wherein the second electrode layer includes: a cylindrical portion on an internal surface of the first insertion layer; and an extension portion extending from the cylindrical portion to cover the upper end of the first electrode layer and the upper end of the first insertion layer. ### Claim 11 (depends on 10) The semiconductor device as claimed in claim 10, wherein the upper electrode includes a portion filling an internal space defined by the cylindrical portion of the second electrode layer. ### Claim 12 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first insertion layer includes a plurality of stacked material layers. ### Claim 13 (depends on 1) The semiconductor device as claimed in claim 1, further comprising: a second insertion layer having a cylindrical shape and surrounding an external surface of the first electrode layer; and a third electrode layer having a cylindrical shape and surrounding an external surface of the second insertion layer. ### Claim 14 (depends on 13) The semiconductor device as claimed in claim 13, wherein the second insertion layer is spaced apart from the first insertion layer. ### Claim 15 (depends on 13) The semiconductor device as claimed in claim 13, wherein an external side surface of the second electrode layer includes a portion vertically aligned with an external side surface of the third electrode layer. ### Claim 16 A semiconductor device, comprising: a substrate; a plurality of lower electrodes on the substrate; a dielectric layer covering the plurality of lower electrodes; and an upper electrode covering the dielectric layer, wherein each of the plurality of lower electrodes includes: a first electrode layer, a second electrode layer on the first electrode layer, and an insertion layer between the first electrode layer and the second electrode layer, the insertion layer being surrounded by the first electrode layer and the second electrode layer, and the insertion layer having a cylindrical shape and including a metal oxide, wherein the insertion layer is spaced apart from the dielectric layer, and wherein an upper end of the insertion layer and an upper end of the first electrode layer are in contact with the second electrode layer. ### Claim 17 (depends on 16) The semiconductor device as claimed in claim 16, wherein: the first electrode layer is in contact with an external surface of the insertion layer, and the second electrode layer is in contact with an internal surface of the insertion layer and extends to cover an upper end of the insertion layer. ### Claim 18 (depends on 16) The semiconductor device as claimed in claim 16, wherein: the first electrode layer and the second electrode layer have tensile stress, and the insertion layer has compressive stress. ### Claim 19 A semiconductor device, comprising: an isolation layer on a substrate, the isolation layer defining active regions; gate electrodes crossing the active regions and extending into the isolation layer; first impurity regions and second impurity regions in the active regions on opposite sides adjacent to the gate electrodes; bit lines on the gate electrodes and the active regions, the bit lines being electrically connected to the first impurity regions; conductive patterns on side surfaces of the bit lines and electrically connected to the second impurity regions; a plurality of lower electrodes extending vertically on the conductive patterns and electrically connected to each of the conductive patterns; at least one supporter layer contacting a side surface of each of the plurality of lower electrodes; a dielectric layer covering the plurality of lower electrodes and the at least one supporter layer; and an upper electrode covering the dielectric layer, wherein each of the plurality of lower electrodes includes: a first electrode layer having a cylindrical shape, an insertion layer on an internal surface of the first electrode layer, having a cylindrical shape, and including a metal oxide, and a second electrode layer on an internal surface of the insertion layer and extending to cover an upper end of the first electrode layer and an upper end of the insertion layer, wherein the insertion layer is spaced apart from the dielectric layer, and wherein an upper end of the insertion layer and an upper end of the first electrode layer are in contact with the second electrode layer. ### Claim 20 (depends on 19) The semiconductor device as claimed in claim 19, wherein: the at least one supporter layer includes a lower supporter layer and an upper supporter layer, the upper supporter layer being at a level higher than a level of the lower supporter layer, the lower supporter layer is in contact with the first electrode layer and is spaced apart from the second electrode layer, and the upper supporter layer is in contact with the second electrode layer.