# US 12,604,488 B2 · Silicon capacitor structure and method of manufacturing the same

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- Number: US 12,604,488 B2
- Document ID: US12604488B2
- Status: Granted
- Kind: B2
- Application number: 18/116,318
- Filed: 2023-03-02
- Published: 2024-03-21
- Granted: 2026-04-14
- Earliest claimed: 2022-09-15
- Assignees: Powerchip Semiconductor Manufacturing Corporation
- Applicants: Powerchip Semiconductor Manufacturing Corporation
- Inventors: Li-Peng Chang; Chih-Ling Hung; San-Jung Chang
- Web page: https://patentgrep.com/patent/US12604488B2

## CPC

- H10D 1/692: {Electrodes}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a silicon capacitor structure, including a substrate, an interlayer dielectric (ILD) layer on the substrate, a capacitor recess extending from a surface of the ILD layer into the substrate, a capacitor in the capacitor recess, wherein the capacitor includes a bottom electrode on a surface of the capacitor recess, a capacitive dielectric layer on a surface of the bottom electrode, and a top electrode on a surface of the capacitive dielectric layer and filling up the capacitor recess.

## Claims

### Claim 1

A method of manufacturing a silicon capacitor structure, comprising:
providing a substrate;
filling a first bottom electrode material in said substrate, wherein a surface of said first bottom electrode material is flush with a front surface of said substrate;
forming semiconductor devices and an interlayer dielectric (ILD) layer on said front surface of said substrate;
filling a second bottom electrode material in said ILD layer, wherein said second bottom electrode material is connected and aligned with said first bottom electrode material;
performing a first etching process to form a through-silicon hole and a capacitor recess, wherein said through-silicon hole extends from said ILD layer into said substrate, and said capacitor recess extends from said second bottom electrode material into said first bottom electrode material, and a depth of said through-silicon hole in said substrate is larger than a depth of said first bottom electrode material in said substrate; and
forming a dielectric layer and a metal layer sequentially in said through-silicon hole and said capacitor recess, wherein said dielectric layer and said metal layer in said through-silicon hole constitute a through-silicon via (TSV), and said dielectric layer and said metal layer in said capacitor recess and said first bottom electrode material and said second bottom electrode material constitute a capacitor.

### Claim 2 (depends on 1)

The method of manufacturing a silicon capacitor structure of claim 1, further comprising performing a backside grinding process after forming said TSV to expose said metal layer of said TSV from a back surface of said substrate without exposing said first bottom electrode material.

### Claim 3 (depends on 2)

The method of manufacturing a silicon capacitor structure of claim 2, further comprising forming redistribution layers on said back surface of said substrate after said backside grinding process, and said redistribution layers are electrically connected with said TSV.

### Claim 4 (depends on 1)

The method of manufacturing a silicon capacitor structure of claim 1, wherein steps of filling said first bottom electrode material comprise:
performing a second etching process to form a first electrode recess in said substrate; and
forming said first bottom electrode material in said first electrode recess.

### Claim 5 (depends on 1)

The method of manufacturing a silicon capacitor structure of claim 1, wherein steps of filling said second bottom electrode material comprise:
performing a third etching process to form a second electrode recess in said ILD layer, and said second electrode recess exposes said first bottom electrode material and is aligned with said first bottom electrode material; and
forming said second bottom electrode material in said second electrode recess.

### Claim 6 (depends on 1)

The method of manufacturing a silicon capacitor structure of claim 1, further comprising forming a sacrificial layer in said first bottom electrode material, wherein said first etching process etches said second bottom electrode material till to said sacrificial layer.

### Claim 7 (depends on 6)

The method of manufacturing a silicon capacitor structure of claim 6, further comprising removing said sacrificial layer to form said capacitor recess.

### Claim 8 (depends on 1)

The method of manufacturing a silicon capacitor structure of claim 1, further comprising:
filling an insulating layer in said substrate before said first bottom electrode material is formed, wherein a surface of said insulating layer is flush with said front surface of said substrate; and
filling said first bottom electrode material in said insulating layer.

### Claim 9 (depends on 1)

The method of manufacturing a silicon capacitor structure of claim 1, further comprising forming metal interconnects on said ILD layer after said capacitor and said through-silicon hole are formed, and said metal interconnects are electrically connected with said through-silicon hole, said capacitor and said semiconductor devices.