# US 12,604,487 B2 · Semiconductor structure having deep trench capacitor and method of manufacturing thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,487 B2 - Document ID: US12604487B2 - Status: Granted - Kind: B2 - Application number: 18/154,875 - Filed: 2023-01-16 - Published: 2024-05-23 - Granted: 2026-04-14 - Earliest claimed: 2022-11-18 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: Chih-Hsuan Tai; Hsiang-Tai Lu - Web page: https://patentgrep.com/patent/US12604487B2 ## CPC - H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors} - H10D 1/716: {having vertical extensions} - H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 64/01: Manufacture or treatment - H10D 64/20: Electrodes characterised by their shapes, relative sizes or dispositions - H10W 20/42: Vias, e.g. via plugs - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor structure includes a substrate including a recess indented into the substrate, a capacitor structure at least partially disposed within the recess, and an interconnect structure disposed over and electrically connected to the capacitor structure. The capacitor structure includes a first electrode layer, a second electrode layer over the first electrode layer, and a first dielectric between the first electrode layer and the second electrode layer. The first electrode layer includes a first body portion disposed in and conformal to the recess and a first extending portion disposed on the substrate, and the second electrode layer covers the first dielectric, the first body portion and the first extending portion of the first electrode layer. ## Claims ### Claim 1 A semiconductor structure, comprising: a substrate including a recess indented into the substrate; a capacitor structure at least partially disposed within the recess, an interconnect structure disposed over and electrically connected to the capacitor structure, and an isolation layer, wherein the capacitor structure includes a first electrode layer, a second electrode layer over the first electrode layer, and a first dielectric between the first electrode layer and the second electrode layer, the first electrode layer includes a first body portion disposed in and conformal to the recess and a first extending portion disposed on the substrate, and the second electrode layer covers the first dielectric, the first body portion and the first extending portion of the first electrode layer, wherein the isolation layer is disposed between the first electrode layer and the substrate, and wherein the first electrode layer is enclosed by the first dielectric and the isolation layer. ### Claim 2 (depends on 1) The semiconductor structure of claim 1, wherein the first electrode layer and the first dielectric are enclosed by the second electrode layer and the isolation layer. ### Claim 3 (depends on 1) The semiconductor structure of claim 1, wherein the first extending portion of the first electrode layer includes a top surface and a sidewall, the second electrode layer includes a second body portion, a second extending portion and a second protruding portion, the second body portion is disposed in the recess and over the first body portion of the first electrode layer, the second extending portion is disposed over the top surface of the first extending portion of the first electrode layer, and the second protruding portion surrounds the sidewall of the first extending portion of the first electrode layer. ### Claim 4 (depends on 3) The semiconductor structure of claim 3, wherein the second body portion, the second extending portion, and the second protruding portion of the second electrode layer are integral and continuous. ### Claim 5 (depends on 3) The semiconductor structure of claim 3, wherein the second extending portion and the second protruding portion of the second electrode layer form a step structure. ### Claim 6 (depends on 3) The semiconductor structure of claim 3, wherein the capacitor structure further includes a third electrode layer disposed over the second electrode layer, and a second dielectric between the second electrode layer and the third electrode layer. ### Claim 7 (depends on 6) The semiconductor structure of claim 6, wherein the third electrode layer includes a third extending portion disposed over the second extending portion of the second electrode layer, and at least a portion of the second extending portion is exposed from the third extending portion of the third electrode layer. ### Claim 8 (depends on 7) The semiconductor structure of claim 7, wherein the capacitor structure further includes a fourth electrode layer having a fourth extending portion and a fourth protruding portion, the fourth extending portion is disposed over the third extending portion of the third electrode layer, and the fourth protruding portion is disposed over at least a portion of the second extending portion of the second electrode layer and adjacent to the third extending portion of the third electrode layer. ### Claim 9 (depends on 3) The semiconductor structure of claim 3, wherein the second protruding portion of the second electrode layer is in contact with the isolation layer. ### Claim 10 (depends on 1) The semiconductor structure of claim 1, wherein at least a portion of the first dielectric is in contact with the isolation layer. ### Claim 11 A method of manufacturing a semiconductor structure, comprising: forming a recess on a surface of a substrate; disposing an isolation layer on the surface and extending into the recess; forming a capacitor structure at least partially disposed within the recess, wherein the formation of the capacitor structure includes: disposing a first electrode layer over the isolation layer; disposing a first dielectric over the first electrode layer; and disposing a second electrode layer to cover and surround the first dielectric and the first electrode layer; and forming an interconnect structure disposed over and electrically connected to the capacitor structure. ### Claim 12 (depends on 11) The method of claim 11, wherein at least a portion of the second electrode layer is in contact with the isolation layer. ### Claim 13 (depends on 11) The method of claim 11, further comprising: forming a third electrode layer between the isolation layer and the capacitor structure, wherein at least a portion of the third electrode layer is exposed through the capacitor structure. ### Claim 14 (depends on 11) The method of claim 11, further comprising: forming a third electrode layer over the second electrode layer; and forming a fourth electrode layer over and surrounding the third electrode layer. ### Claim 15 A semiconductor structure, comprising: a substrate including a recess indented into the substrate; a capacitor structure at least partially disposed within and conformal to the recess, and an interconnect structure disposed over and electrically connected to the capacitor structure, and an isolation layer, wherein the capacitor structure includes a first electrode layer, a second electrode layer over the first electrode layer, and a third electrode layer disposed over the second electrode layer and the first electrode layer, wherein the first electrode layer and the second electrode layer are separated by a first dielectric, and the second electrode layer and the third electrode layer are separated by a second dielectric, wherein the isolation layer is disposed between the first electrode layer and the substrate, and wherein the first electrode layer is enclosed by the first dielectric and the isolation layer. ### Claim 16 (depends on 15) The semiconductor structure of claim 15, wherein the third electrode layer includes an extending portion disposed over the second electrode layer and a protruding portion surrounding a sidewall of the second electrode layer, and the extending portion and the protruding portion of the third electrode layer are integral and continuous. ### Claim 17 (depends on 16) The semiconductor structure of claim 16, wherein the protruding portion of the third electrode layer has an L shape. ### Claim 18 (depends on 15) The semiconductor structure of claim 15, wherein the first electrode layer includes a first body portion disposed in the recess and a first extending portion disposed on the substrate, the second electrode layer includes a second body portion disposed over the first body portion of the first electrode layer and a second extending portion disposed over a portion of the first extending portion of the first electrode layer; and the third electrode layer includes a third extending portion disposed over a top surface of the second electrode layer and a third protruding portion disposed adjacent to a sidewall of the second electrode layer. ### Claim 19 (depends on 18) The semiconductor structure of claim 18, wherein the third electrode layer further includes a fourth protruding portion connected to the third protruding portion and disposed adjacent to a sidewall of the first extending portion of the first electrode layer, and the third extending portion, the third protruding portion and the fourth protruding portion of the third electrode layer are integral and continuous. ### Claim 20 (depends on 15) The semiconductor structure of claim 15, wherein the capacitor structure further includes a fourth electrode layer disposed over the third electrode layer, and a fifth electrode layer disposed over and surrounding the fourth electrode layer, wherein the fourth electrode layer is enclosed by the third electrode layer and the fifth electrode layer.