Cross point array architecture for multiple decks
AssigneeMicron Technology, Inc.
InventorsAgostino Pirovano, Lorenzo Fratin
Life of this patent
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Abstract
Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.
Claims20
An apparatus, comprising:
- a tile of a memory array, the tile of the memory array comprising a plurality of memory cells of the memory array addressable via a plurality of access lines, the plurality of access lines comprising a first access line and a second access line;
- and
- a plurality of access line decoders positioned beneath the memory array, wherein a first access line decoder of the plurality of access line decoders is coupled with respective first access line segments of the first access line using a first plurality of sockets located at respective ends of the respective first access line segments and a second access line decoder of the plurality of access line decoders is coupled with respective second access line segments of the second access line using a second plurality of sockets located in respective middle locations of the respective second access line segments.
A method, comprising:
- identifying at least one cell of a memory array, the memory array comprising a tile comprising a plurality of memory cells of the memory array addressable via a plurality of access lines, the plurality of access lines comprising a first access line and a second access line;
- and
- accessing the at least one cell of the memory array using a plurality of access line decoders positioned beneath the memory array, wherein a first access line decoder of the plurality of access line decoders is coupled with respective first access line segments of the first access line using a first plurality of sockets located at respective ends of the respective first access line segments and a second access line decoder of the plurality of access line decoders is coupled with respective second access line segments of the second access line using a second plurality of sockets located in respective middle locations of the respective second access line segments.
An apparatus, comprising:
- a tile of a memory array, the tile of the memory array comprising a plurality of memory cells of the memory array addressable via a plurality of access lines, the plurality of access lines comprising a first access line and a second access line;
- and
- a plurality of access line decoders positioned beneath the memory array, wherein a first access line decoder of the plurality of access line decoders is coupled with a plurality of first segments of the first access line using a first plurality of sockets, wherein respective ends of the plurality of first segments that are farthest from a socket are each located a first distance from a socket of the first plurality of sockets, wherein a second access line decoder of the plurality of access line decoders is coupled with a plurality of second segments of the second access line using a second plurality of sockets, wherein respective ends of the plurality of second segments that are farthest from a socket are each located the first distance from a socket of the second plurality of sockets, and wherein respective lengths of the plurality of first segments are different from respective lengths of the plurality of second segments.
Dependencies are inferred from the claim text.