# US 12,604,481 B2 · IC's with multple levels of embedded memory

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- Number: US 12,604,481 B2
- Document ID: US12604481B2
- Status: Granted
- Kind: B2
- Application number: 17/558,446
- Filed: 2021-12-21
- Published: 2023-06-22
- Granted: 2026-04-14
- Earliest claimed: 2021-12-21
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Wilfred Gomes; Abhishek Anil Sharma; Uygar Avci
- Web page: https://patentgrep.com/patent/US12604481B2

## CPC

- H10B 53/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 53/30: characterised by the memory core region
- H10B 53/40: characterised by the peripheral circuit region
- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10D 1/682: {having dielectrics comprising perovskite structures}
- H10W 72/90: Bond pads, in general
- H10W 90/00: Package configurations
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10B 12/315: {with the capacitor higher than a bit line}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10W 72/01: {Manufacture or treatment}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Integrated circuits with embedded memory having multiple levels. Each memory array level includes ferroelectric capacitors coupled to an array of thin film access transistors according to a 1T-1F or 1T-many F bit-cell architecture. The levels of embedded memory are monolithically fabricated, one over the other, or after monolithically fabricating one level of embedded memory in a host IC structure, a second IC structure with another level of memory array is directly bonded to a front or backside of the host IC structure in a face-to-face or face-to-back orientation. The second IC structure may include additional peripheral CMOS circuitry, such as sense amps or decoders, or not.

## Claims

### Claim 1

An integrated circuit (IC) die, comprising:
first field effect transistors (FETs) with monocrystalline channel material; and
an embedded memory array structure coupled to the first FETs, wherein the embedded memory array structure comprises:
a first array level on a front side of the first FETs, the first array level comprising capacitors and thin film transistors (TFTs) coupled thereto, wherein each of the capacitors in the first array level comprises a first conductor and a second conductor with a ferroelectric material therebetween; and
a second array level on a back side of the first FETs, the second array level comprising capacitors and TFTs coupled thereto, in a vertical stack with the first array level, and with the first FETs between the first array level and the second array level, wherein each of the capacitors in the second array level comprises a first conductor and a second conductor with the ferroelectric material therebetween.

### Claim 2 (depends on 1)

The IC die of claim 1, further comprising one or more first levels of metallization between the first FETs and the first array level.

### Claim 3 (depends on 2)

The IC die of claim 2, further comprising a hybrid bond interface (HBI) between a first metal feature on the back side of the first FETs and a second metal feature of one or more second levels of metallization located between the first FETs and the second array level.

### Claim 4 (depends on 3)

The IC die of claim 3, further comprising second FETs having a monocrystalline channel material, the second FETs separated from the first FETs by the second array level with one or more third levels of metallization between the second FETs and the second array level.

### Claim 5 (depends on 4)

The IC die of claim 4, wherein the first FETs are part of sense amp circuitry for the first level of capacitors and TFTs, and wherein the second FETs are part of sense amp circuitry for the second level of capacitors and TFTs.

### Claim 6 (depends on 3)

The IC die of claim 3, wherein at least some of the first FETs are coupled to the second array level through the second levels of metallization.

### Claim 7 (depends on 6)

The IC die of claim 6, wherein a first subset of the first FETs are part of sense amp circuitry for the first array level, and a second subset of the first FETs are part of sense amp circuitry for the second array level.

### Claim 8 (depends on 6)

The IC die of claim 6, further comprising second FETs having a monocrystalline channel material, the second FETs separated from the first FETs by the second array level with one or more third levels of metallization between the second FETs and the second array level.

### Claim 9 (depends on 8)

The IC die of claim 8, wherein the second FETs are part of decoder circuitry for the second level of capacitors and TFTs.

### Claim 10 (depends on 1)

The IC die of claim 1, wherein:
the first array level comprises an array of 1T-1F bit-cells; and
the second array level comprises an array of 1T-1F bit-cells.

### Claim 11 (depends on 10)

The IC die of claim 10, wherein:
the first array level comprises an array of 1T-xF bit-cells, where x is an integer number greater than one; and
the second array level comprises an array of 1T-xF bit-cells, where x is an integer number greater than one.

### Claim 12 (depends on 1)

The IC die of claim 1, wherein:
the ferroelectric material comprises predominantly Hf, O, and one or impurity dopants that comprise at least one of Si or Ge.

### Claim 13 (depends on 1)

A system comprising:
the IC die of claim 1;
and
a power supply coupled to the IC die to power the IC die.

### Claim 14 (depends on 13)

The system of claim 13, wherein:
the IC die includes at least one of microprocessor core circuitry or floating point gate array (FPGA) circuitry.