# US 12,604,480 B2 · Ferroelectric memory device and method of forming the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,604,480 B2
- Document ID: US12604480B2
- Status: Granted
- Kind: B2
- Application number: 18/152,597
- Filed: 2023-01-10
- Published: 2024-01-11
- Granted: 2026-04-14
- Earliest claimed: 2022-07-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Meng-Han Lin; Bo-Feng Young; Sai-Hooi Yeong; Chi On Chui
- Web page: https://patentgrep.com/patent/US12604480B2

## CPC

- H10B 51/30: characterised by the memory core region
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/689: {having ferroelectric layers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A device includes a memory layer over a substrate; a first source/drain structure and a second source/drain structure on the memory layer, wherein the first source/drain structure and the second source drain structure each include a first source/drain layer on the memory layer; a second source/drain layer on the first source/drain layer, wherein the second source/drain layer is different from the first source/drain layer; and a metal layer on the second source/drain layer; and a channel region extending on the memory layer from the first source/drain layer of the first source/drain structure to the first source/drain layer of the second source/drain structure.

## Claims

### Claim 1

A method comprising:
forming a first conductive feature in a first dielectric layer;
depositing a memory layer on the first conductive feature;
depositing a channel layer on the memory layer;
depositing a second dielectric layer on the channel layer;
etching a first opening and a second opening in the second dielectric layer to expose the channel layer;
etching the channel layer exposed by the first opening and the second opening to expose the memory layer, wherein a remaining region of the channel layer extends between the first opening and the second opening;
depositing a first source/drain layer in the first opening and the second opening, wherein the first source/drain layer physically contacts the remaining region;
depositing a second source/drain layer on the first source/drain layer in the first opening and the second opening; and
depositing a conductive material on the second source/drain layer in the first opening and the second opening.

### Claim 2 (depends on 1)

The method of claim 1 further comprising etching the first source/drain layer prior to depositing the second source/drain layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein etching the first source/drain layer exposes the memory layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein depositing the first source/drain layer forms a defect in the first source/drain layer near the remaining region.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second source/drain layer is free of defects.

### Claim 6 (depends on 1)

The method of claim 1, wherein etching the channel layer forms recesses underneath the second dielectric layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the second source/drain layer has a different doping concentration than the first source/drain layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first source/drain layer and the second source/drain layer comprise the same material.

### Claim 9

A method comprising:
forming a word line over a substrate;
forming a ferroelectric layer over the word line;
forming a channel region over the ferroelectric layer; and
forming a bit line and a source line on opposite sidewalls of the channel region, wherein forming the bit line and the source line comprises:
depositing a first oxide semiconductor layer on the ferroelectric layer and on the opposite sidewalls of the channel region;
etching the first oxide semiconductor layer, wherein portions of the first oxide semiconductor layer remain on the opposite sidewalls of the channel region after the etching;
depositing a second oxide semiconductor layer over the ferroelectric layer and the remaining portions of the first oxide semiconductor layer; and
depositing a conductive material over the second oxide semiconductor layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein depositing the first oxide semiconductor layer comprises a conformal deposition process.

### Claim 11 (depends on 9)

The method of claim 9, wherein the first oxide semiconductor layer comprises indium gallium zinc oxide.

### Claim 12 (depends on 9)

The method of claim 9, wherein the first oxide semiconductor layer comprises a defect extending from a sidewall of the channel region to a top surface of the first oxide semiconductor layer.

### Claim 13 (depends on 9)

The method of claim 9, wherein etching the first oxide semiconductor layer exposes the ferroelectric layer.

### Claim 14 (depends on 9)

The method of claim 9 further comprising depositing an insulating layer over the channel region, wherein the remaining portions of the first oxide semiconductor layer protrude underneath the insulating layer.

### Claim 15 (depends on 9)

The method of claim 9, wherein the opposite sidewalls of the channel region are curved.

### Claim 16

A method comprising:
forming a memory layer over a substrate;
forming a channel region on the memory layer; and
forming a first source/drain structure and a second source/drain structure on the memory layer, wherein forming the first source/drain structure and the second source drain structure each comprise:
forming a first source/drain layer on the memory layer, wherein the
channel region extends on the memory layer from the first source/drain layer of the first source/drain structure to the first source/drain layer of the second source/drain structure;
forming a second source/drain layer on the first source/drain layer, wherein the second source/drain layer is different from the first source/drain layer; and
forming a metal layer on the second source/drain layer
wherein at least one of the first source/drain layer or second source/drain layer is an oxide semiconductor material.

### Claim 17 (depends on 16)

The method of claim 16, wherein the second source/drain layer has a thickness in the range of 2 nm to 20 nm.

### Claim 18 (depends on 16)

The method of claim 16 wherein the second source/drain layer is thicker than the first source/drain layer.

### Claim 19 (depends on 16)

The method of claim 16, wherein the memory layer comprises an oxide material comprising hafnium.

### Claim 20 (depends on 1)

The method of claim 1, wherein the memory layer is a ferroelectric layer.