# US 12,604,478 B2 · Semiconductor memory device and electronic system including the same

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- Number: US 12,604,478 B2
- Document ID: US12604478B2
- Status: Granted
- Kind: B2
- Application number: 18/474,307
- Filed: 2023-09-26
- Published: 2024-04-11
- Granted: 2026-04-14
- Earliest claimed: 2022-10-11
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: So Hyun Lee; Kang-Oh Yun; Dong Jin Lee; Jun Hee Lim
- Web page: https://patentgrep.com/patent/US12604478B2

## CPC

- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory device includes: a substrate including a first region and a second region, the first region includes a peripheral circuit and a first active region (FAR), and the second region includes memory cell blocks. The FAR includes a FAR first extension extending in a first direction, a FAR second extension extending in a second direction, and a FAR third extension extending in a third direction. The FAR first extension, the FAR second extension, and the FAR third extension form an angle greater than 90 degrees relative to one another. The device includes a first pass transistor circuit configured to transmit driving signals, and the first pass transistor circuit includes a FAR first gate structure on the FAR first extension, a FAR second gate structure on the FAR second extension, a FAR third gate structure on the FAR third extension, and a first shared source/drain.

## Claims

### Claim 1

A semiconductor memory device comprising:
a substrate including a first region and a second region, wherein:
the first region includes a peripheral circuit and a first active region (FAR);
the second region includes memory cell blocks;
the FAR includes a FAR first extension extending in a first direction, a FAR second extension extending in a second direction, and a FAR third extension extending in a third direction, and
the FAR first extension, the FAR second extension, and the FAR third extension form respective angles greater than 90 degrees relative to one another; and
a first pass transistor circuit configured to transmit driving signals such that operating voltages are applied to the memory cell blocks, wherein the first pass transistor circuit includes:
a FAR first gate structure on the FAR first extension, a FAR second gate structure on the FAR second extension, and a FAR third gate structure on the FAR third extension, and
a first shared source/drain between the FAR first gate structure, the FAR second gate structure, and the FAR third gate structure.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the memory cell blocks include a first memory cell block, a second memory cell block, a third memory cell block, and wherein the first pass transistor circuit further includes a first pass transistor, a second pass transistor, and a third pass transistor configured to transmit the driving signals such that the operating voltages are applied to the first memory cell block, the second memory cell block, and the third memory cell block, respectively.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1, wherein the first pass transistor circuit further includes a first individual source/drain on the FAR first extension, a second individual source/drain on the FAR second extension, and a third individual source/drain on the FAR third extension.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1, wherein the FAR is Y-shaped.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
a second active region (SAR) defined in the first region of the substrate and spaced apart from the FAR; and
a second pass transistor circuit in the SAR and spaced apart from the first pass transistor circuit, wherein:
the SAR includes a SAR first extension extending in the first direction, a SAR second extension extending in the second direction, and a SAR third extension extending in the third direction,
the second pass transistor circuit includes a SAR first gate structure on the SAR first extension, a SAR second gate structure on the SAR second extension, a SAR third gate structure on the SAR third extension, and a second shared source/drain between the SAR first gate structure, the SAR second gate structure, and the SAR third gate structure.

### Claim 6 (depends on 5)

The semiconductor memory device of claim 5, wherein:
a center of the FAR defines a recess, and
one of the SAR first extension, the SAR second extension, and the SAR third extension corresponds to the recess.

### Claim 7 (depends on 5)

The semiconductor memory device of claim 5, wherein:
the substrate extends in a first horizontal direction and a second horizontal direction that is orthogonal to the first horizontal direction, and
the first and second shared sources/drains are aligned in the first direction.

### Claim 8 (depends on 5)

The semiconductor memory device of claim 5, further comprising:
a third active region (TAR) defined in the first region of the substrate and spaced apart from the FAR and the SAR; and
a third pass transistor circuit in the TAR and spaced apart from the first pass transistor circuit and the second pass transistor circuit, wherein:
the TAR includes a TAR first extension extending in the first direction, a TAR second extension extending in the second direction, and a TAR third extension extending in the third direction, and
the third pass transistor circuit includes a TAR first gate structure on the TAR first extension, a TAR second gate structure on the TAR second extension, and a TAR third gate structure on the TAR third extension, and a third shared source/drain.

### Claim 9 (depends on 8)

The semiconductor memory device of claim 8, wherein
the FAR and the SAR are in a Y shape and have a side-by-side arrangement,
the FAR and the TAR are in the Y shape and have the side-by-side arrangement, and
a distance between the first shared source/drain and the second shared source/drain, a distance between the second shared source/drain and the third shared source/drain, and a distance between the first shared source/drain and the third shared source/drain are equal.

### Claim 10 (depends on 8)

The semiconductor memory device of claim 8, wherein
the FAR and the SAR are in a Y shape and have an inverted arrangement,
the FAR and the TAR are in the Y shape and have the inverted arrangement, and
a distance between the first shared source/drain and the second shared source/drain and a distance between the first shared source/drain and the third shared source/drain are equal.

### Claim 11 (depends on 8)

The semiconductor memory device of claim 8, further comprising:
a fourth active region (FoAR) defined in the first region of the substrate and spaced apart from the FAR, the SAR, and the TAR; and
a fourth pass transistor circuit in the FoAR and spaced apart from the first pass transistor circuit, the second pass transistor circuit, and the third pass transistor circuit, wherein:
the FoAR includes a FoAR first extension extending in the first direction, a FoAR second extension extending in the second direction, and a FoAR third extension extending in the third direction, and
the fourth pass transistor circuit includes a FoAR first gate structure on the FoAR first extension, a FoAR second gate structure on the FoAR second extension, and a FoAR third gate structure on the FoAR third extension, and a fourth shared source/drain.

### Claim 12 (depends on 11)

The semiconductor memory device of claim 11, wherein
the FAR and the SAR are in a Y shape and have a side-by-side arrangement,
the FAR and the FoAR are in the Y shape and have the side-by-side arrangement,
a first distance between the first shared source/drain and the second shared source/drain and a second distance between the first shared source/drain and the fourth shared source/drain are equal, and
a third distance between the first shared source/drain and the third shared source/drain is different from the first distance or the second distance.

### Claim 13 (depends on 11)

The semiconductor memory device of claim 11, wherein
the FAR and the SAR are in a Y shape and have an inverted arrangement,
the TAR and the FoAR are in the Y shape and have the inverted arrangement,
the SAR and the TAR are in the Y shape and have a side-by-side arrangement,
the FAR and the FoAR are in the Y shape and have the side-by-side arrangement, and
a distance between the first shared source/drain and the second shared source/drain, a distance between the second shared source/drain and the third shared source/drain, a distance between the third shared source/drain and the fourth shared source/drain, and a distance between the first shared source/drain and the fourth shared source/drain are equal.

### Claim 14

A semiconductor memory device comprising:
a first substrate including a first surface that extends in a first horizontal direction and a second horizontal direction that is orthogonal to the first horizontal direction, and a memory cell region on the first surface; and
a second substrate including a second surface that is below the first substrate, a first peripheral circuit region on the second surface and configured to receive a block selection signal and to transmit a driving signal to the memory cell region,
wherein the first peripheral circuit region includes a first active region, the first active region including a first gate structure extending in a first direction, a second gate structure extending in a second direction, a third gate structure extending in a third direction, and a first shared drain between the first gate structure, the second gate structure, and the third gate structure, and
wherein the first direction, the second direction, and the third direction are not parallel to one another and are spaced apart from one another.

### Claim 15 (depends on 14)

The semiconductor memory device of claim 14, wherein the first active region includes a first extension, a second extension, and a third extension that form respective angles of 120 degrees relative to one another.

### Claim 16 (depends on 14)

The semiconductor memory device of claim 14, wherein the first peripheral circuit region and the memory cell region are connected by bonding first bonding pads on the first substrate and second bonding pads on the second substrate, and wherein the first surface of the first substrate and the second surface of the second substrate face each other.

### Claim 17 (depends on 14)

The semiconductor memory device of claim 14, wherein:
the memory cell region includes gate electrode layers that extend in the first horizontal direction and are stacked in a vertical direction, and the memory cell region includes channel structures that extend in the vertical direction and penetrate the gate electrode layers, and
each of the channel structures includes an information storage film, a semiconductor pattern, and a variable resistance film that are sequentially stacked on sidewalls of channel holes that penetrate the gate electrode layers.

### Claim 18 (depends on 17)

The semiconductor memory device of claim 17, wherein:
a second peripheral circuit region is on the second substrate and is spaced apart from the first peripheral circuit region,
the second peripheral circuit region includes a second active region, the second active region including a fourth gate structure extending in the first direction, a fifth gate structure extending in the second direction, and a sixth gate structure extending in the third direction, the fourth gate structure, the fifth gate structure, and the sixth gate structure spaced apart from one another,
a second shared drain between the fourth gate structure, the fifth gate structure, and the sixth gate structure and
the first and second shared drains are aligned in the first direction.

### Claim 19 (depends on 18)

The semiconductor memory device of claim 18, wherein the first active region and the second active region are in a Y shape and have a side-by-side arrangement.

### Claim 20

An electronic system comprising:
a main substrate;
a semiconductor memory device on the main substrate, the semiconductor memory device including a first substrate that includes a peripheral circuit and a second substrate that includes memory cells; and
a controller on the main substrate, the controller being electrically connected to the semiconductor memory device, wherein:
the semiconductor memory device includes an active region that is defined on the first substrate, the active region includes a first extension extending in a first direction, a second extension extending in a second direction, and a third extension extending in a third direction, the first extension, the second extension, and the third extension forming respective angles greater than 90 degrees relative to one another, the active region includes a pass transistor circuit configured to transmit driving signals such that operating voltages are applied to the memory cells, and
the pass transistor circuit includes a first gate structure on the first extension, a second gate structure on the second extension, a third gate structure on the third extension, and a shared source/drain between the first gate structure, the second gate structure, and the third gate structure.