# US 12,604,475 B2 · Memory structure and manufacturing method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,604,475 B2
- Document ID: US12604475B2
- Status: Granted
- Kind: B2
- Application number: 17/990,738
- Filed: 2022-11-21
- Published: 2024-04-04
- Granted: 2026-04-14
- Earliest claimed: 2022-09-29
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chia-Wen Wang; Chien-Hung Chen; Chia-Hui Huang; Ling Hsiu Chou; Jen Yang Hsueh; Chih-Yang Hsu
- Web page: https://patentgrep.com/patent/US12604475B2

## CPC

- H10B 43/30: characterised by the memory core region
- H10B 41/30: characterised by the memory core region
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

## Claims

### Claim 1

A memory structure, comprising:
a substrate;
a first doped region located in the substrate;
a second doped region located in the substrate;
a first gate located on the first doped region;
a second gate located on the second doped region;
a first charge storage structure located between the first gate and the first doped region and comprising:
a first tunneling dielectric layer located on the substrate;
a first dielectric layer located on the first tunneling dielectric layer; and
a first charge storage layer located between the first dielectric layer and the first tunneling dielectric layer;
a second charge storage structure located between the second gate and the second doped region and comprising:
a second tunneling dielectric layer located on the substrate;
a second dielectric layer located on the second tunneling dielectric layer; and
a second charge storage layer located between the second dielectric layer and the second tunneling dielectric layer, wherein
a thickness of the second tunneling dielectric layer is greater than a thickness of the first tunneling dielectric layer; and
an amorphous region located in the substrate above the second doped region, wherein the amorphous region is adjacent to a top surface of the substrate.

### Claim 2 (depends on 1)

The memory structure according to claim 1, wherein the first doped region and the second doped region are separated from each other.

### Claim 3 (depends on 1)

The memory structure according to claim 1, wherein a ratio of the thickness of the second tunneling dielectric layer to the thickness of the first tunneling dielectric layer is greater than 1 and less than or equal to 1.35.

### Claim 4 (depends on 1)

The memory structure according to claim 1, wherein a top of the second tunneling dielectric layer is higher than a top of the first tunneling dielectric layer.

### Claim 5 (depends on 1)

The memory structure according to claim 1, wherein the second tunneling dielectric layer is in direct contact with the amorphous region.

### Claim 6 (depends on 1)

The memory structure according to claim 1, wherein there is a dopant in the amorphous region, and the dopant comprises a group IVA element.

### Claim 7 (depends on 6)

The memory structure according to claim 6, wherein the dopant comprises germanium.

### Claim 8 (depends on 1)

The memory structure according to claim 1, further comprising:
a well region located in the substrate, wherein the first doped region and the second doped region are located in the well region.

### Claim 9 (depends on 1)

The memory structure according to claim 1, further comprising:
a third gate located on the substrate, wherein the third gate is adjacent to the first gate;
a third dielectric layer located between the third gate and the substrate;
a fourth gate located on the substrate, wherein the fourth gate is adjacent to the second gate; and
a fourth dielectric layer located between the fourth gate and the substrate.