# US 12,604,474 B2 · Trench patterning process using microcracking > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,474 B2 - Document ID: US12604474B2 - Status: Granted - Kind: B2 - Application number: 18/475,826 - Filed: 2023-09-27 - Published: 2025-03-27 - Granted: 2026-04-14 - Earliest claimed: 2023-09-27 - Assignees: SanDisk Technologies LLC - Applicants: Western Digital Technologies, Inc. - Inventors: Motoki Kawasaki; Shunsuke Takuma; Seiji Shimabukuro - Web page: https://patentgrep.com/patent/US12604474B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/10: characterised by the top-view layout - H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 63/10: Phase change RAM [PCRAM, PRAM] devices - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A method includes forming a first-tier structure over a substrate, forming first-tier trenches laterally extending along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction through the first-tier structure, non-conformally depositing a plurality of material layers over the first-tier structure such that first-tier cavities are formed in volumes of the first-tier trenches that are not filled with the plurality of material layers, and inducing laterally-extending cracks in portions of the plurality of material layers that overlie the first-tier cavities, such that the laterally-extending cracks are connected to a respective underlying one of the first-tier cavities and vertically extend to a topmost material layer of the plurality of material layers. ## Claims ### Claim 1 A method, comprising: forming a first-tier structure over a substrate; forming first-tier trenches laterally extending along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction through the first-tier structure; non-conformally depositing a plurality of material layers over the first-tier structure such that first-tier cavities are formed in volumes of the first-tier trenches that are not filled with the plurality of material layers; and inducing laterally-extending cracks in portions of the plurality of material layers that overlie the first-tier cavities, wherein the laterally-extending cracks are connected to a respective underlying one of the first-tier cavities and vertically extend to a topmost material layer of the plurality of material layers. ### Claim 2 (depends on 1) The method of claim 1, wherein the laterally-extending cracks are induced by performing an anneal process at an elevated temperature. ### Claim 3 (depends on 2) The method of claim 2, further comprising performing an anisotropic etch process after formation of the laterally-extending cracks, wherein the laterally-extending cracks are converted into second-tier trenches that are adjoined to a respective one of the first-tier trenches. ### Claim 4 (depends on 3) The method of claim 3, wherein the materials of the plurality of material layers that are deposited in the first-tier trenches are removed by the anisotropic etch process. ### Claim 5 (depends on 3) The method of claim 3, wherein a total thickness of the plurality of material layers located above a topmost horizontal surface of the first-tier structure is at least 10 times a maximum lateral width of the first-tier trenches. ### Claim 6 (depends on 3) The method of claim 3, wherein the plurality of material layers comprise a second-tier structure comprising an alternating stack of insulating layers and sacrificial material layers. ### Claim 7 (depends on 6) The method of claim 6, wherein: the insulating layers comprise silicon oxide layers; and the sacrificial material layers comprise hydrogen-containing silicon nitride layers. ### Claim 8 (depends on 7) The method of claim 7, wherein an atomic ratio of hydrogen atoms to silicon atoms in the hydrogen-containing silicon nitride layers is in a range from 0.05 to 0.20 prior to the inducing the laterally-extending cracks. ### Claim 9 (depends on 7) The method of claim 7, wherein: the laterally-extending cracks are induced by performing an anneal process at an elevated temperature in a nitrogen-containing ambient; and the anneal process reduces hydrogen content in the hydrogen-containing silicon nitride layers. ### Claim 10 (depends on 6) The method of claim 6, further comprising: forming laterally-extending cavities by removing the sacrificial material layers selective to the insulating layers; forming electrically conductive layers in the laterally-extending cavities by conformally depositing an electrically conductive material in the laterally-extending cavities; and removing portions of the electrically conductive material from volumes of the first-tier trenches and the second-tier trenches, such that the electrically conductive layers are electrically isolated from each other. ### Claim 11 (depends on 6) The method of claim 6, further comprising: forming a pair of crack-stop trenches at ends of the first-tier cavities; and filling the pair of crack-stop trenches with a pair of crack-stop structures comprising a carbon or a semiconductor material. ### Claim 12 (depends on 11) The method of claim 11, wherein one of the laterally-extending cracks stops at the pair of crack-stop structures. ### Claim 13 (depends on 11) The method of claim 11, further comprising: forming memory openings through the second-tier structure and the first-tier structure; and depositing a set of conformal material layers in the memory openings and in the pair of crack-stop trenches, wherein: memory opening fill structures comprise first portions of the set of conformal material layers that fill the memory openings; the pair of crack-stop structures comprise second portions of the set of conformal material layers that fill the pair of crack-stop trenches; and the set of conformal material layers comprise, in order of deposition, a blocking dielectric layer, a memory material layer, a tunneling dielectric layer, a semiconductor channel material layer, and a dielectric core layer. ### Claim 14 (depends on 6) The method of claim 6, wherein non-uniformities are located in the alternating stack above the first-tier cavities. ### Claim 15 (depends on 14) The method of claim 14, wherein the non-uniformities comprise microcracks. ### Claim 16 (depends on 14) The method of claim 14, wherein the non-uniformities comprise recesses. ### Claim 17 (depends on 14) The method of claim 14, wherein the non-uniformities comprise structurally weak regions. ### Claim 18 (depends on 14) The method of claim 14, further comprising forming wedges in an upper portion of the second-tier structure above the non-uniformities. ### Claim 19 (depends on 6) The method of claim 6, further comprising: non-conformally depositing a plurality of additional material layers over the second-tier structure such that second-tier cavities are formed in volumes of the second-tier trenches that are not filled with the plurality of additional material layers; and inducing additional laterally-extending cracks in portions of the plurality of additional material layers that overlie the second-tier cavities, wherein the additional laterally-extending cracks are connected to a respective underlying one of the second-tier cavities and vertically extend to a topmost material layer among the plurality of additional material layers. ### Claim 20 (depends on 19) The method of claim 19, further comprising: expanding the additional laterally-extending cracks into third-tier trenches by performing an anisotropic etch process; forming memory openings through patterned portions of the plurality of additional material layers, the first-tier structure, and the first-tier structure; and forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and a vertical semiconductor channel.