# US 12,604,471 B2 · Semiconductor memory device and manufacturing method of semiconductor memory device

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- Number: US 12,604,471 B2
- Document ID: US12604471B2
- Status: Granted
- Kind: B2
- Application number: 17/972,859
- Filed: 2022-10-25
- Published: 2023-11-23
- Granted: 2026-04-14
- Earliest claimed: 2022-05-19
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Kun Young Lee
- Web page: https://patentgrep.com/patent/US12604471B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/10: characterised by the top-view layout
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device may include a stack structure including a plurality of conductive layers, a hole formed in the stack structure, a memory layer allowing a first part and a second part of the hole to be spaced apart from each other in the hole, and a first channel layer disposed in the first part of the hole and a second channel layer disposed in the second part of the hole.

## Claims

### Claim 1

A semiconductor memory device comprising:
a stack structure including a plurality of conductive layers, each of the plurality of conductive layers having a surface facing a first direction and the plurality of conductive layers being spaced apart from each other in the first direction;
a hole formed in the stack structure, the hole including a first part and second part that are adjacent to each other in a second direction that is perpendicular to the first direction, wherein the hole has a width that is narrower closer to a connection point between the first part and the second part;
a first channel layer in the first part of the hole;
a second channel layer in the second part of the hole; and
a memory layer interposed between the first channel layer and the second channel layer and extending into a space between the stack structure and each of the first and second channel layers, and
wherein the memory layer separates the first and second channel layers.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, further comprising a first insulating pillar and a second insulating pillar, penetrating the stack structure at both sides of the connection point between the first part and the second part of the hole.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2, wherein the hole is concave in a region in contact with the first insulating pillar and the second insulating pillar.

### Claim 4 (depends on 2)

The semiconductor memory device of claim 2, wherein the memory layer is formed along a sidewall of each of the first insulating pillar and the second insulating pillar to have a concave shape based on a contour of the first insulating pillar and the second insulating pillar.

### Claim 5 (depends on 2)

The semiconductor memory device of claim 2, wherein, in the first direction, a length of each of the first channel layer and the second channel layer is greater than a length of each of the first insulating pillar and the second insulating pillar.

### Claim 6 (depends on 1)

The semiconductor memory device of claim 1, wherein the plurality of conductive layers includes a protrusion part protruding toward the connection point.

### Claim 7 (depends on 6)

The semiconductor memory device of claim 6, wherein the hole is concave in a region in contact with the protrusion part of the plurality of conductive layers.

### Claim 8 (depends on 6)

The semiconductor memory device of claim 6, wherein the memory layer is formed along the protrusion part of the plurality of conductive layers.

### Claim 9 (depends on 1)

The semiconductor memory device of claim 1, wherein edges of the first part and the second part of the hole overlap with an edge of a hypothetical circle.

### Claim 10 (depends on 1)

The semiconductor memory device of claim 1, wherein edges of the first part and the second part of the hole overlap with an edge of a hypothetical ellipse.

### Claim 11 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
a first bit line connected to the first channel layer;
a second bit line connected to the second channel layer; and
a doped semiconductor structure connected to the first channel layer and the second channel layer.

### Claim 12 (depends on 1)

The semiconductor memory device of claim 1, further comprising a first core insulating layer and a second core insulating layer,
wherein the first channel layer surrounds the first core insulating layer, and
wherein the second channel layer surrounds the second core insulating layer.

### Claim 13

A semiconductor memory device comprising:
a stack structure including a plurality of conductive layers that are spaced apart from each other;
a butterfly-shaped hole formed in the stack structure;
a memory layer extending along a sidewall of the butterfly-shaped hole, the memory layer isolating a first region and a second region in the butterfly-shaped hole;
a first channel layer in the first region; and
a second channel layer in the second region, and
wherein the memory layer separates the first and second channel layers.

### Claim 14 (depends on 13)

The semiconductor memory device of claim 13,
wherein the memory layer fills a central region of the butterfly-shaped hole between the first channel layer and the second channel layer and peripheral regions of the butterfly-shaped hole between the stack structure and each of the first channel layer and the second channel layer.

### Claim 15 (depends on 13)

The semiconductor memory device of claim 13, further comprising an insulating pillar in contact with a concave portion of the butterfly-shaped hole, the insulating pillar penetrating the stack structure.

### Claim 16 (depends on 15)

The semiconductor memory device of claim 15, wherein, in a stacking direction of the plurality of conductive layers, a length of each of the first channel layer and the second channel layer is greater than a length of the insulating pillar.

### Claim 17 (depends on 13)

The semiconductor memory device of claim 13, wherein the plurality of conductive layers include a protrusion part protruding toward a concave portion of the butterfly-shaped hole.

### Claim 18 (depends on 13)

The semiconductor memory device of claim 13, further comprising:
a first bit line connected to the first channel layer;
a second bit line connected to the second channel layer; and
a doped semiconductor structure connected to the first channel layer and the second channel layer.

### Claim 19 (depends on 13)

The semiconductor memory device of claim 13, further comprising a first core insulating layer and a second core insulating layer,
wherein the first channel layer surrounds the first core insulating layer, and
wherein the second channel layer surrounds the second core insulating layer.