# US 12,604,468 B2 · Vertical NOR memory strings and method for fabrication thereof

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- Number: US 12,604,468 B2
- Document ID: US12604468B2
- Status: Granted
- Kind: B2
- Application number: 17/559,101
- Filed: 2021-12-22
- Published: 2022-07-21
- Granted: 2026-04-14
- Earliest claimed: 2021-01-20
- Assignees: Sunrise Memory Corporation
- Applicants: Sunrise Memory Corporation
- Inventors: Vinod Purayath; Kenta Ohama; Yosuke Nosho
- Web page: https://patentgrep.com/patent/US12604468B2

## CPC

- H10B 43/10: characterised by the top-view layout
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A VNOR memory string includes: (a) first and second pillars embedded in multiple composite layers, each composite layer comprising an insulator layer and a conductor layer, the first and second pillars each comprising a first semiconductor material of a first conductivity; (b) a second semiconductor layer of a second conductivity type opposite the first conductivity type on the outside of third pillar also embedded in the composite layers, the third pillar contacting both the first and second pillars; and (c) a storage layer provided between the second semiconductor layer and each of the conductor layer in the composite layers.

## Claims

### Claim 1

A VNOR memory string, comprising:
a plurality of first and second pillars embedded in multiple composite layers that are formed above a planar surface of a semiconductor substrate, each composite layer comprising an insulator layer and a conductor-containing layer, wherein each conductor-containing layer comprises a conductor and wherein the each of the first pillars and the second pillars comprise a first semiconductor layer of a first conductivity;
a plurality of third pillars also embedded in the composite layers, each third pillar being formed between a pair of the first and the second pillars;
a second semiconductor layer of a second conductivity type opposite the first conductivity type provided on the sidewall of each third pillar, the second semiconductor layer contacting both the first and second pillars that are formed on the sides of the respective third pillar;
a storage layer provided conformally in the conductor-containing layer of each composite layer, such that a portion of the storage layer is provided between the second semiconductor layer and the conductor in each conductor-containing layer, and such that the storage layers of different ones of the composite layers are separated from each other, and each portion of the storage layer encircles the first, second and third pillars within each conductor-containing layer and is separated from different ones of the portions of the storage layer encircling other sets of first, second and third pillars; and
a third insulator layer encircling each of the first and second pillars except at a portion where each of the first and second pillars contacts the respective second semiconductor layer formed on the third pillar, wherein the third insulator layer is provided between the respective first or second pillar and the storage layer without intervening layers.

### Claim 2 (depends on 1)

The VNOR memory string of claim 1, wherein each of the third pillars further comprises a second insulator layer enclosed by the second semiconductor layer.

### Claim 3 (depends on 1)

The VNOR memory string of claim 1, wherein the insulator layers in the composite layers each comprise silicon oxide.

### Claim 4 (depends on 1)

The VNOR memory string of claim 1, wherein the first semiconductor layer and the second semiconductor layer comprise n+ polysilicon and p− polysilicon, respectively.

### Claim 5 (depends on 1)

The VNOR memory string of claim 1, wherein the storage layer comprises a charge-trapping layer.

### Claim 6 (depends on 5)

The VNOR memory string of claim 5, wherein the charge-trapping layer comprises a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.

### Claim 7 (depends on 1)

The VNOR memory string of claim 1, wherein the conductor layers of the composite layers each comprise metallic tungsten (W) in conjunction with a titanium nitride (TiN) liner.

### Claim 8 (depends on 1)

The VNOR memory string of claim 1, further comprising an isolation layer and a conductor-filled via formed therein, the conductor-filled via contacting the first semiconductor layer in one of the first and second pillars in each set of the first and second pillars.

### Claim 9 (depends on 8)

The VNOR memory string of claim 8, further comprising an etch-stop layer above a conductor layer in the composite layers.

### Claim 10 (depends on 1)

The VNOR memory string of claim 1, wherein each of the third pillars extends into the insulator layer of the composite layers closest to the planar surface of the semiconductor substrate.

### Claim 11 (depends on 1)

The VNOR memory string of claim 1, wherein each of the plurality of the first and second pillars extend into the semiconductor substrate.

### Claim 12 (depends on 1)

The VNOR memory string of claim 1, wherein circuitry for supporting memory operations are formed at or near the planar surface of semiconductor substrate.

### Claim 13 (depends on 1)

The VNOR memory string of claim 1, wherein the second semiconductor layer is provided on the sidewall of each third pillar and is removed at a bottom of the respective third pillar.