# US 12,604,465 B2 · Semiconductor device

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- Number: US 12,604,465 B2
- Document ID: US12604465B2
- Status: Granted
- Kind: B2
- Application number: 18/376,022
- Filed: 2023-10-03
- Published: 2024-04-18
- Granted: 2026-04-14
- Earliest claimed: 2022-10-12
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Junhyeok Ahn; Sohyun Park
- Web page: https://patentgrep.com/patent/US12604465B2

## CPC

- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/482: {Bit lines}
- H10B 12/02: {for one transistor one-capacitor [1T-1C] memory cells}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/485: {Bit line contacts}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device includes a substrate having an active region; a bit line structure on the substrate and extending in one direction; a bit line contact electrically connecting a first impurity region of the active region and the bit line structure; and a storage node contact disposed on a sidewall of the bit line structure and electrically connected to a second impurity region of the active region, wherein the storage node contact includes a vertical extension portion extending in a vertical direction, perpendicular to an upper surface of the substrate, and a horizontal extension portion integrally connected to the vertical extension portion and extending in a horizontal direction, parallel to the upper surface of the substrate.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate including an active region;
a bit line structure on the substrate and extending in one direction;
a bit line contact electrically connecting a first impurity region of the active region and the bit line structure; and
a storage node contact on a sidewall of the bit line structure and electrically connected to a second impurity region of the active region, the storage node contact including:
a vertical extension portion extending in a vertical direction, the vertical direction being perpendicular to an upper surface of the substrate, and
a horizontal extension portion integrally connected to the vertical extension portion and extending in a horizontal direction, the horizontal direction being parallel to the upper surface of the substrate.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the horizontal extension portion is at a level lower than a lower surface of the bit line structure.

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the horizontal extension portion is in contact with at least a portion of an upper surface of the active region.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, wherein an entirety of the horizontal extension portion overlaps the second impurity region of the active region in the vertical direction.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising a device isolation layer defining the active region, an upper surface of the device isolation layer being at a level higher than an upper surface of the active region.

### Claim 6 (depends on 5)

The semiconductor device as claimed in claim 5, wherein:
an upper surface of the horizontal extension portion is at a same level as the upper surface of the device isolation layer, and
a lower surface of the horizontal extension portion is at a same level as the upper surface of the active region.

### Claim 7 (depends on 5)

The semiconductor device as claimed in claim 5, further comprising a sacrificial pattern layer on the active region, an upper surface of the sacrificial pattern layer being coplanar with the upper surface of the device isolation layer, and the sacrificial pattern layer being in contact with the horizontal extension portion.

### Claim 8 (depends on 7)

The semiconductor device as claimed in claim 7, wherein the sacrificial pattern layer includes at least one of a metal, a metal oxide, a metal nitride, or a semiconductor material that is different from a material of the substrate.

### Claim 9 (depends on 5)

The semiconductor device as claimed in claim 5, wherein the horizontal extension portion is in contact with at least a portion of a side surface of the device isolation layer protruding from the active region in the vertical direction.

### Claim 10 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the vertical extension portion includes a protrusion protruding beyond a lower surface of the horizontal extension portion.

### Claim 11 (depends on 10)

The semiconductor device as claimed in claim 10, further comprising a spacer structure surrounding a sidewall of the bit line contact, the spacer structure being in contact with the protrusion.

### Claim 12 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising a spacer structure between the bit line structure and the storage node contact, at least a portion of the horizontal extension portion overlapping the spacer structure in the vertical direction.

### Claim 13 (depends on 12)

The semiconductor device as claimed in claim 12, wherein the spacer structure includes a first spacer, a second spacer, and a third spacer sequentially stacked on the sidewall of the bit line structure, the horizontal extension portion including a portion overlapping the second spacer in the vertical direction.

### Claim 14

A semiconductor device, comprising:
a substrate including an active region, the active region having a first impurity region and a second impurity region;
a sacrificial pattern layer on the active region;
a device isolation layer defining the active region, an upper surface of the device isolation layer being coplanar with an upper surface of the sacrificial pattern layer;
a word line structure extending in a first horizontal direction, an upper surface of the word line structure being coplanar with the upper surface of the sacrificial pattern layer;
a bit line structure on the substrate and extending in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction;
a bit line contact electrically connecting the first impurity region and the bit line structure; and
a storage node contact on a side surface of the bit line contact and electrically connected to the second impurity region, the storage node contact including a horizontal extension portion contacting an upper surface of the second impurity region and extending in the first horizontal direction.

### Claim 15 (depends on 14)

The semiconductor device as claimed in claim 14, wherein the horizontal extension portion is at a same level as the sacrificial pattern layer.

### Claim 16 (depends on 14)

The semiconductor device as claimed in claim 14, wherein the sacrificial pattern layer includes a portion on the first impurity region, the portion contacting the side surface of the bit line contact.

### Claim 17 (depends on 14)

The semiconductor device as claimed in claim 14, wherein the sacrificial pattern layer includes a first layer and a second layer on the active region, the first layer including silicon oxide, and the second layer including at least one of a metal, a metal oxide, a metal nitride, or silicon germanium.

### Claim 18

A semiconductor device, comprising:
a substrate including an active region, the active region having a first impurity region and a second impurity region;
a sacrificial pattern layer on the active region, the sacrificial pattern layer including at least one of a metal, a metal oxide, a metal nitride, or silicon germanium;
a device isolation layer defining the active region, an upper surface of the device isolation layer being coplanar with an upper surface of the sacrificial pattern layer;
a word line structure extending in a first horizontal direction, an upper surface of the word line structure being coplanar with the upper surface of the sacrificial pattern layer;
a bit line structure on the substrate and extending in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction; and
a bit line contact electrically connecting the first impurity region and the bit line structure, the sacrificial pattern layer including a portion on the first impurity region that is in contact with a side surface of the bit line contact.

### Claim 19 (depends on 18)

The semiconductor device as claimed in claim 18, wherein:
the active region includes a first active region and a second active region spaced apart from each other,
the bit line contact includes a first bit line contact connected to a first impurity region of the first active region, and
a first spacer structure disposed on a sidewall of the first bit line contact has a portion contacting a side surface of a second impurity region of the second active region, the first spacer structure being on a sidewall of the bit line structure.

### Claim 20 (depends on 19)

The semiconductor device as claimed in claim 19, further comprising a storage node contact having:
a vertical extension portion on a sidewall of the first spacer structure and extending in a vertical direction, the vertical direction being perpendicular to an upper surface of the substrate, and
a horizontal extension portion integrally connected to the vertical extension portion and extending in a horizontal direction, the horizontal direction being parallel to the upper surface of the substrate, and the horizontal extension portion being at a level higher than a contact point between the first spacer structure and the second active region.