# US 12,604,463 B2 · Memory device having ultra-lightly doped region and manufacturing method thereof

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- Number: US 12,604,463 B2
- Document ID: US12604463B2
- Status: Granted
- Kind: B2
- Application number: 18/368,669
- Filed: 2023-09-15
- Published: 2024-06-13
- Granted: 2026-04-14
- Earliest claimed: 2022-12-09
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Chung-Lin Huang
- Web page: https://patentgrep.com/patent/US12604463B2

## CPC

- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/488: {Word lines}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present application provides a memory device having an ultra-lightly doped region and a manufacturing method of the memory device. The memory device includes a semiconductor substrate including a word line extending into the semiconductor substrate, wherein the semiconductor substrate is defined with a source region, a drain region and an ultra-lightly doped region under the drain region, the word line is disposed between the source region and the drain region, and the ultra-lightly doped region is disposed at a sidewall of the word line.

## Claims

### Claim 1

A memory device, comprising:
a semiconductor substrate including a word line extending into the semiconductor substrate and a plug extending into the semiconductor substrate and disposed adjacent to the word line,
wherein the semiconductor substrate is defined with a source region, a drain region opposite to the source region, and an ultra-lightly doped region under the drain region, the word line is disposed between the source region and the drain region, and the ultra-lightly doped region is disposed at a sidewall of the word line;
wherein the ultra-lightly doped region includes a first ultra-lightly doped region having a first conductivity type and a second ultra-lightly doped region having a second conductivity type different from the first conductivity type;
wherein a length of the word line is substantially greater than or equal to a depth of the ultra-lightly doped region.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein the first ultra-lightly doped region is disposed above the second ultra-lightly doped region.

### Claim 3 (depends on 1)

The memory device according to claim 1, wherein the first conductivity type is N-type, and the second conductivity type is P-type.

### Claim 4 (depends on 1)

The memory device according to claim 1, wherein the word line includes a gate oxide extending into the semiconductor substrate, a gate electrode disposed on the gate oxide, a buffering dielectric conformal to the gate oxide and on the gate electrode, and a capping dielectric surrounded by the buffering dielectric.

### Claim 5 (depends on 4)

The memory device according to claim 4, wherein the ultra-lightly doped region is adjacent to a bottom portion of the buffering dielectric, and the buffering dielectric contacts the gate electrode and the capping dielectric.