# US 12,604,462 B2 · Semiconductor structure having word line and manufacturing method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,604,462 B2
- Document ID: US12604462B2
- Status: Granted
- Kind: B2
- Application number: 17/822,126
- Filed: 2022-08-24
- Published: 2024-02-29
- Granted: 2026-04-14
- Earliest claimed: 2022-08-24
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Chiang-Lin Shih; Yu-Ting Lin
- Web page: https://patentgrep.com/patent/US12604462B2

## CPC

- H10B 12/05: {Making the transistor}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/036: {the capacitor extending under the transistor}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/33: {the capacitor extending under the transistor}
- H10B 12/488: {Word lines}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor structure includes a first dielectric layer, a second dielectric layer on the first dielectric layer, a capacitor structure in the first dielectric layer and the second dielectric layer, a third dielectric layer on the second dielectric layer, a word line, a channel structure, and a gate dielectric. The word line is located in the third dielectric layer and extends across the capacitor structure. The channel structure is located in the third dielectric layer and surrounds the word line and a portion of the third dielectric layer. The gate dielectric has a first portion and a second portion separated from the first portion, wherein the first portion is between a sidewall of the word line and the channel structure, and the second portion is between an inner sidewall of the third dielectric layer and the channel structure.

## Claims

### Claim 1

A semiconductor structure, comprising:
a first dielectric layer;
a second dielectric layer located on the first dielectric layer;
a capacitor structure located in the first dielectric layer and the second dielectric layer, and comprising a semiconductor material;
a third dielectric layer located on the second dielectric layer;
a word line located in the third dielectric layer and extending across the capacitor structure, wherein a portion of the third dielectric layer is between the word line and the capacitor structure, and said portion of the third dielectric layer, the word line, and the capacitor structure are aligned with each other;
a channel structure located in the third dielectric layer and surrounding the word line and said portion of the third dielectric layer;
a source region between a top of the capacitor structure and a bottom of said portion of the third dielectric layer, wherein a top of said portion of the third dielectric layer and the bottom of said portion of the third dielectric layer are respectively in direct contact with a bottom of the word line and a top of the source region, and an orthogonal projection of the entire said portion of the third dielectric layer and an orthogonal projection of the entire word line on the top of the capacitor structure completely overlap with each other and are only located on the semiconductor material of the capacitor structure; and
a gate dielectric having a first portion and a second portion separated from the first portion, wherein the first portion is between a sidewall of the word line and the channel structure, and the second portion is between an inner sidewall of the third dielectric layer and the channel structure.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first portion of the gate dielectric extends to a sidewall of said portion of the third dielectric layer.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein a bottom of the first portion of the gate dielectric is in contact with the source region.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein a bottom of the second portion of the gate dielectric is in contact with the source region.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein a bottom of the channel structure is in contact with the source region.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the channel structure is surrounded by the second portion of the gate dielectric.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the capacitor structure further comprises:
a first electrode surrounding the semiconductor material;
a high-k dielectric surrounding the first electrode; and
a second electrode surrounding a bottom portion of the high-k dielectric.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a drain region located on a top of the channel structure.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, further comprising:
a bit line electrically connected to the drain region.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, further comprising:
a landing pad between the drain region and the bit line.

### Claim 11 (depends on 9)

The semiconductor structure of claim 9, further comprising:
a fourth dielectric layer located on the bit line; and
a fifth dielectric layer located on the fourth dielectric layer, wherein a material of the fifth dielectric layer is different from a material of the fourth dielectric layer.

### Claim 12 (depends on 1)

The semiconductor structure of claim 1, wherein a width of the bottom of the word line is greater than a width of a top of the word line.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the top of the word line is in contact with the channel structure.

### Claim 14

A manufacturing method of a semiconductor structure, comprising:
forming a capacitor structure in a first dielectric layer and a second dielectric layer that is located on the first dielectric layer, wherein the capacitor structure comprises a semiconductor material;
forming a source region on a top of the capacitor structure;
forming a third dielectric layer and a word line on the second dielectric layer, wherein the word line is located in the third dielectric layer and extends across the capacitor structure, wherein a portion of the third dielectric layer is between the word line and the capacitor structure;
forming a channel hole in the third dielectric layer to expose the word line, wherein said portion of the third dielectric layer, the word line, and the capacitor structure are aligned with each other, and the source region is between the top of the capacitor structure and a bottom of said portion of the third dielectric layer, and a top of said portion of the third dielectric layer and the bottom of said portion of the third dielectric layer are respectively in direct contact with the a bottom of the word line and a top of the source region, and an orthogonal projection of the entire said portion of the third dielectric layer and an orthogonal projection of the entire word line on the top of the capacitor structure completely overlap with each other and are only located on the semiconductor material of the capacitor structure;
forming a first portion and a second portion of a gate dielectric respectively on a sidewall of the word line and an inner sidewall of the third dielectric layer; and
forming a channel structure in the channel hole of the third dielectric layer, wherein the channel structure surrounds the word line and said portion of the third dielectric layer.

### Claim 15 (depends on 14)

The manufacturing method of the semiconductor structure of claim 14, wherein forming the third dielectric layer and the word line on the second dielectric layer is performed such that a width of the bottom of the word line is greater than a width of a top of the word line.

### Claim 16 (depends on 14)

The manufacturing method of the semiconductor structure of claim 14, wherein forming the first portion and the second portion of the gate dielectric is performed such that the first portion of the gate dielectric extends to a sidewall of said portion of the third dielectric layer.

### Claim 17 (depends on 14)

The manufacturing method of the semiconductor structure of claim 14, wherein forming the channel hole in the third dielectric layer comprises etching the third dielectric layer by using an enchant having a high etch selectivity between the third dielectric layer and the word line.

### Claim 18 (depends on 14)

The manufacturing method of the semiconductor structure of claim 14, wherein forming the third dielectric layer and the word line on the second dielectric layer is performed such that the word line has a width in a range from 10 nm to 12 nm.

### Claim 19 (depends on 14)

The manufacturing method of the semiconductor structure of claim 14, wherein forming the channel hole in the third dielectric layer is performed such that the channel hole has a diameter is in a range from 40 nm to 44 nm.