# US 12,604,460 B2 · Semiconductor memory device

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- Number: US 12,604,460 B2
- Document ID: US12604460B2
- Status: Granted
- Kind: B2
- Application number: 18/088,642
- Filed: 2022-12-26
- Published: 2024-02-15
- Granted: 2026-04-14
- Earliest claimed: 2022-08-12
- Assignees: Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicants: Fujian Jinhua Integrated Circuit Co., Ltd.
- Inventors: Yincong Hong; Chia-Hung Wang; Yue Liu; Chung-Ping Hsia
- Web page: https://patentgrep.com/patent/US12604460B2

## CPC

- H10B 12/315: {with the capacitor higher than a bit line}
- H10D 1/716: {having vertical extensions}
- H10B 12/033: {the capacitor extending over the transistor}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/50: {Peripheral circuit region structures}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor memory device includes a substrate, and a plurality of contact pads and a capacitor array structure disposed on an array region of the substrate. The capacitor array structure includes a plurality of capacitors respectively disposed on the contact pads and a middle supporting layer extending laterally between waist portions of the capacitors to define an upper portion and a lower portion of each of the capacitors. The lower portions of the capacitors near the edge of the array region are tilted. The upper portions of the capacitors near the edge of the array region have misalignments to the contact pads. The stress in the capacitor array structure of the semiconductor memory device may be reduced.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a substrate comprising at least an array region;
a peripheral region bordering an edge of the array region;
a plurality of contact pads disposed on the array region; and
a capacitor array structure disposed on the array region, and comprising:
a plurality of capacitors respectively disposed on the contact pads; and
a middle supporting layer extending laterally between waist portions of the capacitors to define an upper portion and a lower portion of each of the capacitors, wherein the lower portions of the capacitors near the edge of the array region are tilted, and the upper portions of the capacitors near the edge of the array region have misalignments to the contact pads, wherein distances of the misalignments are larger as the capacitors closer to the edge of the array region.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein distances of the misalignments are smaller than a pitch of the contact pads and larger than ½ of a space between sidewalls of the contact pads.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, wherein upper axial lines of the upper portions of the capacitors near the edge of the array region are straight and perpendicular to a surface of the substrate.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1, wherein lower axial lines of the lower portions of the capacitors near the edge of the array region are bending.

### Claim 5 (depends on 1)

The semiconductor memory device according to claim 1, further comprising an upper supporting layer extending laterally between top portions of the capacitors.

### Claim 6 (depends on 5)

The semiconductor memory device according to claim 5, wherein the middle supporting layer and the upper supporting layer are made of a same material and comprise a same stress.

### Claim 7 (depends on 1)

The semiconductor memory device according to claim 1, wherein the substrate comprises another array region at a side of the peripheral region opposite to the array region, the semiconductor memory device further comprises:
another capacitor array structure disposed on the another array region; and
a planarization layer on the substrate and filling a space between the capacitor array structure and the another capacitor array structure.

### Claim 8 (depends on 7)

The semiconductor memory device according to claim 7, wherein a portion of the planarization layer between the capacitor array structure and the another capacitor array structure have a trapezoid cross-sectional profile.

### Claim 9

A semiconductor memory device, comprising:
a substrate comprising at least an array region;
a peripheral region bordering an edge of the array region;
a plurality of contact pads disposed on the array region; and
a capacitor array structure disposed on the array region, and comprising:
a plurality of capacitors respectively disposed on the contact pads; and
a middle supporting layer extending laterally between waist portions of the capacitors to define an upper portion and a lower portion of each of the capacitors, wherein the upper portions of the capacitors near the edge of the array region are tilted and have misalignments to the contact pads, wherein distances of the misalignments are larger as the capacitors closer to the edge of the array region.

### Claim 10 (depends on 9)

The semiconductor memory device according to claim 9, wherein distances of the misalignments are smaller than a pitch of the contact pads and larger than ½ of a space between sidewalls of the contact pads.

### Claim 11 (depends on 9)

The semiconductor memory device according to claim 9, wherein lower axial lines of the lower portions of the capacitors near the edge of the array region are straight and perpendicular to a surface of the substrate.

### Claim 12 (depends on 9)

The semiconductor memory device according to claim 9, wherein upper axial lines of the upper portions of the capacitors near the edge of the array region are bending.

### Claim 13 (depends on 9)

The semiconductor memory device according to claim 9, further comprising an upper supporting layer extending laterally between top portions of the capacitors.

### Claim 14 (depends on 13)

The semiconductor memory device according to claim 13, wherein the middle supporting layer and the upper supporting layer are made of different materials and comprise different stresses.

### Claim 15 (depends on 9)

The semiconductor memory device according to claim 9, wherein the substrate comprises another array region at a side of the peripheral region opposite to the array region, the semiconductor memory device further comprises:
another capacitor array structure disposed on the another array region; and
a planarization layer covering the substrate in a blanket manner and filling a space between the capacitor array structure and the another capacitor array structure.

### Claim 16 (depends on 15)

The semiconductor memory device according to claim 15, wherein a portion of the planarization layer between the capacitor array structure and the another capacitor array structure have a trapezoid cross-sectional profile.

### Claim 17

A semiconductor memory device, comprising:
a substrate comprising at least an array region;
a peripheral region bordering an edge of the array region;
a plurality of contact pads disposed on the array region; and
a capacitor array structure disposed on the array region, and comprising:
a plurality of capacitors respectively disposed on the contact pads; and
a middle supporting layer extending laterally between waist portions of the capacitors to define an upper portion and a lower portion of each of the capacitors, wherein the lower portions of the capacitors near the edge of the array region are tilted, and the upper portions of the capacitors near the edge of the array region have misalignments to the contact pads, wherein distances of the misalignments are smaller than a pitch of the contact pads and larger than ½ of a space between sidewalls of the contact pads.

### Claim 18 (depends on 17)

The semiconductor memory device according to claim 17, wherein upper axial lines of the upper portions of the capacitors near the edge of the array region are straight and perpendicular to a surface of the substrate.

### Claim 19 (depends on 17)

The semiconductor memory device according to claim 17, wherein lower axial lines of the lower portions of the capacitors near the edge of the array region are bending.

### Claim 20 (depends on 17)

The semiconductor memory device according to claim 17, further comprising an upper supporting layer extending laterally between top portions of the capacitors.

### Claim 21

A semiconductor memory device, comprising:
a substrate comprising at least an array region;
a peripheral region bordering an edge of the array region;
a plurality of contact pads disposed on the array region; and
a capacitor array structure disposed on the array region, and comprising:
a plurality of capacitors respectively disposed on the contact pads; and
a middle supporting layer extending laterally between waist portions of the capacitors to define an upper portion and a lower portion of each of the capacitors, wherein the upper portions of the capacitors near the edge of the array region are tilted and have misalignments to the contact pads, wherein distances of the misalignments are smaller than a pitch of the contact pads and larger than ½ of a space between sidewalls of the contact pads.

### Claim 22 (depends on 21)

The semiconductor memory device according to claim 21, wherein lower axial lines of the lower portions of the capacitors near the edge of the array region are straight and perpendicular to a surface of the substrate.

### Claim 23 (depends on 21)

The semiconductor memory device according to claim 21, wherein upper axial lines of the upper portions of the capacitors near the edge of the array region are bending.

### Claim 24 (depends on 21)

The semiconductor memory device according to claim 21, further comprising an upper supporting layer extending laterally between top portions of the capacitors.