# US 12,604,457 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,457 B2 - Document ID: US12604457B2 - Status: Granted - Kind: B2 - Application number: 18/459,978 - Filed: 2023-09-01 - Published: 2024-03-07 - Granted: 2026-04-14 - Earliest claimed: 2022-09-05 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Takafumi Masuda; Mutsumi Okajima; Nobuyoshi Saito; Keiji Ikeda - Web page: https://patentgrep.com/patent/US12604457B2 ## CPC - H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells} - H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells} - H10B 12/02: {for one transistor one-capacitor [1T-1C] memory cells} - H10B 12/03: {Making the capacitor or connections thereto} - H10B 12/482: {Bit lines} - H10B 12/488: {Word lines} - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor memory device comprises: a first memory layer; and a first via wiring and a second via wiring extending in a first direction, and having different positions from each other in a second direction. The first memory layer comprises: a first transistor electrically connected to the first via wiring; a memory portion electrically connected to the first transistor; a first wiring electrically connected to the first transistor; a second transistor electrically connected to the second via wiring and the first wiring; a first electrode electrically connected to the second transistor; and a second electrode electrically connected to the first wiring and first electrode. A length of the second electrode in the first direction is larger than one or both of a length of the first wiring in the first direction and a length of the first conductive layer in the first direction. ## Claims ### Claim 1 A semiconductor memory device comprising: a substrate; a first memory layer separated from the substrate in a first direction intersecting a surface of the substrate; and a first via wiring and a second via wiring that extend in the first direction, and have different positions from each other in a second direction intersecting the first direction, wherein the first memory layer comprises: a first transistor which is electrically connected to the first via wiring; a memory portion which is electrically connected to the first transistor; a first wiring which is electrically connected to the first transistor, and extends in the second direction; a second transistor which is electrically connected to the second via wiring, and is electrically connected to the first wiring; a first electrode which is electrically connected to the second transistor; and a second electrode which is electrically connected to the first wiring and the first electrode, the first electrode includes a first conductive layer and a second conductive layer that are arranged in the first direction, the second conductive layer includes a conductive oxide, and a length of the second electrode in the first direction is larger than one or both of a length of the first wiring in the first direction and a length of the first conductive layer in the first direction. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the memory portion is a capacitor. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the first transistor comprises: a first semiconductor layer which is electrically connected to the memory portion and the first via wiring; a first gate electrode which is connected to the first wiring, and faces the first semiconductor layer; and a first gate insulating film which is provided between the first semiconductor layer and the first gate electrode, and the first semiconductor layer faces at least one of surfaces on one side or the other side in the first direction of the first gate electrode. ### Claim 4 (depends on 3) The semiconductor memory device according to claim 3, wherein the first semiconductor layer includes an oxide semiconductor. ### Claim 5 (depends on 3) The semiconductor memory device according to claim 3, wherein the first semiconductor layer includes: at least one element of gallium (Ga) or aluminum (Al); indium (In); zinc (Zn); and oxygen (O). ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, wherein the second transistor comprises: a second semiconductor layer which is electrically connected to the first electrode and the second via wiring; a second gate electrode which faces the second semiconductor layer; and a second gate insulating film which is provided between the second semiconductor layer and the second gate electrode, and the second semiconductor layer faces at least one of surfaces on one side or the other side in the first direction of the second gate electrode. ### Claim 7 (depends on 6) The semiconductor memory device according to claim 6, wherein the second semiconductor layer includes an oxide semiconductor. ### Claim 8 (depends on 6) The semiconductor memory device according to claim 6, wherein the second semiconductor layer includes: at least one element of gallium (Ga) or aluminum (Al); indium (In); zinc (Zn); and oxygen (O). ### Claim 9 (depends on 1) The semiconductor memory device according to claim 1, wherein the length of the second electrode in the first direction is larger than a length of the first electrode in the first direction. ### Claim 10 (depends on 1) The semiconductor memory device according to claim 1, wherein the second electrode contacts the first conductive layer. ### Claim 11 (depends on 1) The semiconductor memory device according to claim 1 comprising: a first connecting surface which is a connecting surface between the second electrode and the first wiring; and a second connecting surface which is a connecting surface between the second electrode and the first electrode, wherein the first connecting surface and the second connecting surface are arranged in the second direction. ### Claim 12 (depends on 1) The semiconductor memory device according to claim 1, wherein the second electrode comprises: a first portion which is connected to the first wiring; a second portion which is connected to the first electrode; and a third portion which is provided between the first portion and the second portion, and is connected to the first portion and the second portion, and a length of the third portion in a third direction intersecting the first direction and the second direction, is smaller than a length of the first portion in the third direction and a length of the second portion in the third direction. ### Claim 13 (depends on 1) The semiconductor memory device according to claim 1 comprising: a first connecting surface which is a connecting surface between the second electrode and the first wiring; and a second connecting surface which is a connecting surface between the second electrode and the first electrode, wherein the first connecting surface and the second connecting surface are arranged in a third direction intersecting the first direction and the second direction. ### Claim 14 (depends on 1) The semiconductor memory device according to claim 1, wherein the conductive oxide is one of indium tin oxide, indium zinc oxide, ruthenium oxide, and iridium oxide. ### Claim 15 A semiconductor memory device comprising: a substrate; a plurality of memory layers arranged in a first direction intersecting a surface of the substrate; and a first via wiring and a second via wiring that extend in the first direction, and have different positions from each other in a second direction intersecting the first direction, wherein the plurality of memory layers each comprise: a first transistor which is electrically connected to the first via wiring; a memory portion which is electrically connected to the first transistor; a first wiring which is electrically connected to the first transistor, and extends in the second direction; a second transistor which is electrically connected to the second via wiring, and is electrically connected to the first wiring; a first electrode which is electrically connected to the second transistor; and a second electrode which is electrically connected to the first wiring and the first electrode, the first electrode includes a first conductive layer and a second conductive layer that are arranged in the first direction, the second conductive layer includes a conductive oxide, and a length of the second electrode in the first direction is larger than one or both of a length of the first wiring in the first direction and a length of the first conductive layer in the first direction. ### Claim 16 (depends on 15) The semiconductor memory device according to claim 15, wherein the length of the second electrode in the first direction is larger than a length of the first electrode in the first direction. ### Claim 17 (depends on 15) The semiconductor memory device according to claim 15, wherein the second electrode contacts the first conductive layer. ### Claim 18 (depends on 15) The semiconductor memory device according to claim 15, wherein the conductive oxide is one of indium tin oxide, indium zinc oxide, ruthenium oxide, and iridium oxide. ### Claim 19 A semiconductor memory device comprising: a substrate; a first memory layer separated from the substrate in a first direction intersecting a surface of the substrate; and a first via wiring and a second via wiring that extend in the first direction, and have different positions from each other in a second direction intersecting the first direction, wherein the first memory layer comprises: a first transistor which is electrically connected to the first via wiring; a memory portion which is electrically connected to the first transistor; a first wiring which is electrically connected to the first transistor, and extends in the second direction; a second transistor which is electrically connected to the second via wiring, and is electrically connected to the first wiring; and an electrode which is electrically connected to the first wiring, and is electrically connected to the second transistor, and a length of the electrode in the first direction is larger than a length of the first wiring in the first direction. ### Claim 20 (depends on 19) The semiconductor memory device according to claim 19, wherein the conductive oxide is one of indium tin oxide, indium zinc oxide, ruthenium oxide, and iridium oxide.