# US 12,604,456 B2 · Semiconductor device and method for fabricating the same

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- Number: US 12,604,456 B2
- Document ID: US12604456B2
- Status: Granted
- Kind: B2
- Application number: 17/863,991
- Filed: 2022-07-13
- Published: 2023-08-10
- Granted: 2026-04-14
- Earliest claimed: 2022-02-10
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Wan Sup Shin; Seung Wook Ryu; Seung Mi Yeo
- Web page: https://patentgrep.com/patent/US12604456B2

## CPC

- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/05: {Making the transistor}
- H10B 12/482: {Bit lines}
- H10B 12/50: {Peripheral circuit region structures}
- H10B 12/488: {Word lines}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device includes: a substrate; a body recess in the substrate; a body dielectric layer over the body recess; an active layer extending in a direction parallel to the substrate over the substrate; a contact node over an end portion of the active layer and perpendicular to the substrate; and a conductive line coupled to the contact node and extended perpendicular to the substrate.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a body recess in the substrate;
a body dielectric layer over the body recess;
an active layer extending in a direction parallel to the substrate over the substrate;
a contact node over an end portion of the active layer and perpendicular to the substrate; and
a conductive line coupled to the contact node and extended perpendicular to the substrate,
wherein the conductive line has a buried portion in the substrate,
wherein a sidewall and a bottom surface of the buried portion are surrounded by the body dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the active layer includes:
a channel; and
a source/drain region disposed on one side of the channel and coupled to the contact node.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the contact node has a height that fully covers the side of one end of one side of the active layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the contact node includes doped polysilicon.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the active layer includes monocrystalline silicon, polysilicon, germanium, silicon-germanium, Indium Gallium Zinc Oxide, or combinations thereof.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a word line extending in a direction crossing the active layer over the active layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the word line includes a double word line, a single word line, or a gate all-around word line.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the conductive line includes a bit line.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the body dielectric layer includes a plurality of silicon oxides that are formed on a surface of the body recess.

### Claim 10

A semiconductor device, comprising:
a body recess in a substrate;
a body dielectric layer over the body recess;
a transistor extending in a direction parallel to the substrate over the substrate and including an active layer having a first end portion and a second end portion;
a bit line contact node on a sidewall, an upper surface, and a lower surface of the first end portion;
a bit line coupled to the bit line contact node and extended perpendicular to the substrate;
a storage contact node on a sidewall, an upper surface, and a lower surface of the second end portion; and
a capacitor coupled to the second end portion and the storage contact node.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the active layer includes:
a channel;
a first source/drain region disposed on a first side of the channel and coupled to the bit line contact node; and
a second source/drain region disposed on a second side of the channel and coupled to the storage contact node.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein each of the bit line contact node and the storage contact node includes doped polysilicon.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the active layer includes monocrystalline silicon, polysilicon, germanium, silicon-germanium or Indium Gallium Zinc Oxide.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein the capacitor includes a cylindrical storage node coupled to the storage contact node.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, further comprising:
a word line extending in a direction crossing the active layer over the active layer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the word line includes a double word line, a single word line, or a gate-all-around word line.

### Claim 17 (depends on 10)

The semiconductor device of claim 10, wherein the body dielectric layer includes silicon oxide.

### Claim 18

A semiconductor device, comprising:
a substrate including a peripheral circuit portion;
a memory cell array including a bit line, including a contact pad side and a bonding pad side, and extended perpendicular to the substrate;
a first bonding pad coupled to the bonding pad side of the bit line;
a second bonding pad disposed on the peripheral circuit portion and coupled to the first bonding pad;
a body dielectric layer covering the contact pad side of the bit line; and
a conductive pad passing through the body dielectric layer and coupled to the contact pad side of the bit line, wherein the contact pad side of the bit line has a protruding shape to be disposed at a higher level than the memory cell array.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the body dielectric layer includes silicon oxide.