# US 12,604,455 B2 · Semiconductor device and a manufacturing method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,455 B2 - Document ID: US12604455B2 - Status: Granted - Kind: B2 - Application number: 17/420,125 - Filed: 2020-11-17 - Published: 2022-05-19 - Granted: 2026-04-14 - Earliest claimed: 2019-12-10 - Assignees: Changxin Memory Technologies, Inc. - Applicants: ChangXin Memory Technologies, Inc. - Inventors: Ping-Heng Wu - Web page: https://patentgrep.com/patent/US12604455B2 ## CPC - H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells} - H10B 12/488: {Word lines} - H10B 12/50: {Peripheral circuit region structures} - H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)} - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device manufacturing method includes: providing a substrate having a memory cell array area; forming a word line trench; forming a word line conductive layer in the word line trench; forming a photoresist on the substrate surface, and patterning it to protect the word line conductive layer in the contact areas but exposes the word line conductive layer outside the word line contact area, and etching the conductive layer. The resulting thickness of the word line conductive structure in the word line contact area is greater than outside the word line contact area. Thereby the opening of the word line contact hole is reduced. The depth of the window position reduces the process time in forming the contact hole, which reduces the excessive erosion of the sidewalls of contact hole having a shallower opening depth, so to avoid the device short circuit. ## Claims ### Claim 1 A method for manufacturing a semiconductor device, providing a substrate, wherein the substrate comprises a memory cell array area on a first surface and a peripheral circuit area, the peripheral circuit area comprises a transistor active area; forming word line trenches in the memory cell array area; filling the word line trenches with a word line conductive layer, wherein a surface of the word line conductive layer is flush with the first surface of the substrate; forming a photoresist layer on the first surface of the substrate, wherein the photoresist layer is patterned to protect a word line contact area of the word line conductive layer and to expose an area outside the word line contact area of the word line conductive layer; etching the word line conductive layer to form a word line conductive structure, wherein the photoresist layer is used as a mask, the area outside the word line contact area of the word line conductive layer exposed by the photoresist layer is etched to a target depth, wherein the word line conductive structure comprises a first conductive structure located in the word line contact area and a second conductive structure located in the area outside the word line contact area, the first conductive structure of the word line conductive structure has a thickness greater than a thickness of the second conductive structure of the word line conductive structure, and a surface of the word line contact area is flush with the first surface of the substrate, a surface of the word line conductive structure is lower than the first surface of the substrate; removing the photoresist layer; forming an insulating dielectric layer on the first surface of the substrate, wherein the insulating dielectric layer comprises a first insulating dielectric layer on the surface of the word line conductive structure and a second insulating dielectric layer on a surface of the transistor active area, wherein a surface of the first insulating dielectric layer is flush with a surface of the second insulating dielectric layer, the first insulating dielectric layer and the second insulating dielectric layer are formed by a same process; and patterning the first insulating dielectric layer and the second insulating dielectric layer, forming a word line contact hole in the word line contact area and forming an active area contact hole in the transistor active area. ### Claim 2 (depends on 1) The method of claim 1, wherein the word line contact area is located at an end of the word line conductive structure. ### Claim 3 (depends on 1) The method of claim 1, wherein the word line contact holes and the active area contact holes are formed in a same process. ### Claim 4 A semiconductor device, comprising: a substrate, a memory cell array area formed on the substrate, and word line trenches arranged in the memory cell array area and having an interval spaced in between each other; a word line conductive structure, comprising a first conductive structure located in a word line contact area and a second conductive structure located in an area outside the word line contact area; wherein the first conductive structure of the word line conductive structure has a thickness greater than a thickness of the second conductive structure of the word line conductive structure; wherein the substrate further comprises: a peripheral circuit area, comprising a transistor active area; an insulating dielectric layer, comprising a first insulating dielectric layer on a surface of the word line conductive structure and a second insulating dielectric layer on a surface of the transistor active area, wherein a surface of the first insulating dielectric layer is flush with a surface of the second insulating dielectric layer, the first insulating dielectric layer and the second insulating dielectric layer are formed by a same process; a word line contact hole formed in the word line contact area; and an active area contact hole formed in the transistor active area. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the word line contact area is located at an end of the word line conductive structure. ### Claim 6 (depends on 4) The semiconductor device of claim 4, wherein a thickness ratio of the first conductive structure located in the word line contact area to the second conductive structure located in an area outside the word line contact area is in a range from 1.5 to 4.0. ### Claim 7 (depends on 4) The semiconductor device of claim 4, wherein the semiconductor device further comprises a word line contact structure located in the word line contact hole, the word line contact structure is formed on and in direct contact with the word line contact area. ### Claim 8 (depends on 4) The semiconductor device of claim 4, wherein the semiconductor device further comprises an active area contact structure located in the active area contact hole, the active area contact structure is formed on and in direct contact with a source area/a drain area of the transistor active area. ### Claim 9 (depends on 1) The method of claim 1, wherein a thickness ratio of the first conductive structure of the word line conductive structure to the second conductive structure of the word line conductive structure is in a range from 1.5 to 4.0.