# US 12,604,452 B2 · Compact electrical connection that can be used to form an SRAM cell and method of making the same

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- Number: US 12,604,452 B2
- Document ID: US12604452B2
- Status: Granted
- Kind: B2
- Application number: 18/193,557
- Filed: 2023-03-30
- Published: 2023-07-27
- Granted: 2026-04-14
- Earliest claimed: 2018-02-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Kuan Lin; Kuo-Yi Chao; Chang-Ta Yang; Mei-Yun Wang; Ping-Wei Wang
- Web page: https://patentgrep.com/patent/US12604452B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- G11C 11/412: using field-effect transistors only
- H10B 10/18: {Peripheral circuit regions}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 89/10: Integrated device layouts
- H10W 20/0698: {Local interconnections}
- H10W 20/42: Vias, e.g. via plugs
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

## Claims

### Claim 1

An integrated circuit structure comprising:
a substrate;
a first semiconductor active area overlying the substrate;
a second semiconductor active area offset from the first semiconductor active area in a first direction;
a first gate overlying a first channel region in the second semiconductor active area;
a first transistor that includes the first channel region, a first source region adjacent to a first side of the first channel region in the second semiconductor active area, a first drain region adjacent to a second side of the first channel region and the first gate;
a conductive contact that is directly connected to the first drain region of the first transistor, the conductive contact being a first conductive material;
a second gate spaced from the first gate, the second gate directly adjacent to the first drain region of the first transistor, an upper surface of the second gate being lower than an upper surface of the conductive contact;
an expanded conductive via including:
a first conductive portion that extends in a plane from the conductive contact to the second gate; and
a second conductive portion that extends downward from the first conductive portion and is directly connected to the second gate, the second conductive portion being the same material as the first conductive portion; and
a first electrical insulation layer that surrounds the expanded conductive via.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the second conductive portion and the first conductive portion are a continuous layer.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein the first conductive material and a second conductive material of the expanded conductive via are different.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
an insulating structure surrounding the conductive contact.

### Claim 5 (depends on 4)

The integrated circuit structure of claim 4, wherein the insulating structure is a first dielectric material and the first electrical insulation layer is a second dielectric material that is different from the first dielectric material.

### Claim 6 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
a second electrical insulation layer overlying the expanded conductive via and the first electrical insulation layer.

### Claim 7 (depends on 6)

The integrated circuit structure of claim 6, further including a conductive wiring layer overlying the first electrical insulation layer.

### Claim 8 (depends on 7)

The integrated circuit structure of claim 7, wherein the conductive wiring layer is positioned spaced from the expanded conductive via in contact with the first electrical insulation layer and surrounded by the second electrical insulation layer.

### Claim 9 (depends on 1)

The integrated circuit structure of claim 1, wherein the second gate is directly adjacent to the first drain region of the first transistor with no gate intervening therebetween.

### Claim 10

A device, comprising:
a first semiconductor active area;
a first gate directly adjacent to the first semiconductor active area;
a conductive contact that is electrically coupled to the first semiconductor active area;
an expanded conductive via that overlays the conductive contact, the expanded conductive via including:
a first conductive portion that extends in a plane from the conductive contact to the first gate; and
a second conductive portion that extends downward from the first conductive portion and is directly connected to the first gate, the second conductive portion being the same material as the first conductive portion;
a first electrical insulation layer that surrounds the expanded conductive via;
a second semiconductor active area offset from the first semiconductor active area in a first direction;
a first channel region formed by the first gate overlying the second semiconductor active area;
a second gate overlying a second channel region of the first semiconductor active area, the second gate offset from the first gate in a second direction, the second direction being perpendicular to the first direction; and
a first transistor that includes the first channel region, a first source region adjacent to a first side of the first channel region in the second semiconductor active area, and a first drain region adjacent to the second side of the first channel region and the first gate.

### Claim 11 (depends on 10)

The device of claim 10, further comprising:
an electrical insulating structure surrounding the conductive contact.

### Claim 12 (depends on 11)

The device of claim 11, wherein the electrical insulating structure is a first dielectric material and the first electrical insulation layer is a second dielectric material that is different from the first dielectric material.

### Claim 13 (depends on 10)

The device of claim 10, further comprising:
a second transistor that includes the second channel region, a second source region adjacent to a first side of the second channel region in the first semiconductor active area, a second drain region adjacent to the second side of the second channel region and the second gate, the second drain region of the first semiconductor active area being electrically coupled to the conductive contact.

### Claim 14 (depends on 13)

The device of claim 13, further comprising:
a third transistor and a fourth transistor in which the second gate overlays a third channel region of the third transistor and the first gate overlays a fourth channel region of the fourth transistor, and wherein a drain of the third transistor is electrically coupled to the second gate and a drain of the fourth transistor is electrically coupled to the first gate to form a pair of cross-coupled inverters that provide an SRAM cell.

### Claim 15

A device, comprising:
a first semiconductor active area;
a first gate overlapping a second semiconductor active area offset from the first semiconductor active area;
a first channel region formed by the first gate overlying the second semiconductor active area;
a conductive contact that is directly connected to the first semiconductor active area, the conductive contact formed of a first conductive material;
an expanded conductive via that overlays the conductive contact and directly contacts the first gate, electrically coupling the first semiconductor active area to the first gate, the expanded conductive via including:
a first conductive portion that extends in a plane from the conductive contact to the first gate; and
a second conductive portion that extends downward from the first conductive portion and is directly connected to the first gate, the second conductive portion being the same material as the first conductive portion;
a second gate overlying the first semiconductor active area forming a second channel region, the second gate being directly adjacent to a first drain region of the first semiconductor active area;
a first electrical insulation layer that surrounds the expanded conductive via; and
a first transistor that includes the first channel region, a source region adjacent to a first side of the first channel region in the second semiconductor active area, and a second drain region adjacent to a second side of the first channel region and the first gate.

### Claim 16 (depends on 15)

The device of claim 15, further comprising:
an insulation structure surrounding the conductive contact.

### Claim 17 (depends on 16)

The device of claim 16, further comprising:
an etch stop layer between the insulation structure and the first electrical insulation layer, the etch stop layer having an opening overlying the first gate.

### Claim 18 (depends on 15)

The device of claim 15, wherein each of the first and second conductive materials includes tungsten.

### Claim 19 (depends on 15)

The device of claim 15, wherein the first conductive material is different than a second conductive material of the expanded conductive via.

### Claim 20 (depends on 15)

The device of claim 15, comprising:
a second transistor that includes the second channel region, a source region adjacent to a first side of the second channel region in the first semiconductor active area, and the first drain region adjacent to a second side of the second channel region and the second gate.