# US 12,604,101 B2 · Semiconductor device and image processing system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,101 B2 - Document ID: US12604101B2 - Status: Granted - Kind: B2 - Application number: 18/623,841 - Filed: 2024-04-01 - Published: 2024-10-17 - Granted: 2026-04-14 - Earliest claimed: 2023-04-12 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Isao Nagayoshi; Kazuaki Terashima - Web page: https://patentgrep.com/patent/US12604101B2 ## CPC - H04N 23/80: Camera processing pipelines; Components thereof - H04N 23/665: {involving internal camera communication with the image sensor, e.g. synchronising or multiplexing SSIS control signals} - H04N 23/843: {Demosaicing, e.g. interpolating colour pixel values} - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A semiconductor device or image processing system includes n interface circuit and a channel composite circuit. The interface circuit outputs a first packet including the line data of the k-th line included in the image data of the first channel, and then outputs a second packet including the line data of the k-th line included in the image data of the second channel. The channel combination circuit writes, to the memory, the line data of the k-th line included in the image data of the first channel to the first address area, and then writes the line data of the k-th line included in the image data of the second channel to the second address area that is consecutive to the first address area. ## Claims ### Claim 1 A semiconductor device comprising: an interface circuit configured to receive image data of a plurality of channels and configured to output a plurality of packets including the image data of the plurality of channels, the plurality of channels including a first channel and a second channel, image data of the first channel being first channel image data and image data of the second channel being second channel image data, and a channel composite circuit configured to receive the plurality of packets and configured to transmit the image data of the plurality of channels included in the plurality of packets to a memory, wherein the first channel image data and the second channel image data include a plurality of line data, respectively, wherein the interface circuit is configured to output a first packet including a k-th line data of the first channel image data, to output a second packet including a k-th line data of the second channel image data and after outputting the first packet, and wherein the channel composite circuit is configured to transmit the k-th line data of the first channel image data to the memory to store in a first address area, and to transmit the k-th line data of the second channel image data to the memory to store in a second address area following the first address area after the k-th line data of the first channel image data is stored in the memory. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of packets have a format according to MIPI (Mobile Industry Processor Interface) CSI-2 (Camera Serial Interface 2) standard. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the channel composite circuit includes a line stride register that stores a line stride value, the line stride value is larger than a total value of line sizes in the image data of the plurality of channels and is i times of BW, where i is an integer larger or equal to than 1 and BW is bus width of the memory, and where i is the smallest, and wherein the channel composite circuit is configured to write k-th line data of image data of the plurality of channels continuously from a line start address based on LCUNT times of the line stride value, where LCUNT is an integer, and write (k+1)-th line data of image data of the plurality of channels continuously from a line address based on (LCUNT+1) times of the line stride value. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the interface circuit outputs the plurality of packets each including a line data in the image data of the plurality of channels in a predetermined channel order for each line, and wherein the channel composite circuit stores a start address for each channel for the line data in a storage area that is a register or a memory, the start address is a relative address from the line start address for each line and is determined based on the predetermined channel order. ### Claim 5 (depends on 3) The semiconductor device according to claim 3, wherein the interface circuit outputs the plurality of packets each including a line data in the image data of the plurality of channels in a variable channel order for each line, and wherein the channel composite circuit stores a start address for each channel and for each line for the line data in a storage area that is a register or a memory, the start address is a relative address from the line start address for each line and is determined by recognizing the variable channel order for each line. ### Claim 6 (depends on 2) The semiconductor device according to claim 2, wherein the channel composite circuit includes: a packet identifying circuit provided in common to the image data of the plurality of channels and configured to identify a channel to which each of the plurality of packets belongs based on a header information of each packet, and a data extract circuit provided in common to the image data of the plurality of channels and configured to extract the line data included in each packet. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the header information includes a virtual channel value and a data type value, and wherein the packet identifying circuit configured to identify the channel to which each of the plurality of packet belongs based on a combination of the virtual channel value and the data type value. ### Claim 8 An image processing system comprising: an image sensor configured to capture image of an object and generates image data of a plurality of channels, the plurality of channels including a first channel and a second channel; a memory storing the image data of the plurality of channels; an interface circuit configured to receive the image data of the plurality of channels and configured to output a plurality of packet including the image data of the plurality of channels; a channel composite circuit configured to receive the plurality of packets and configured to write the image data of the plurality of channels included in the plurality of packets into the memory; and an image signal processor (ISP) configured to perform a demosaicing processing for the image data of the plurality of channel stored in the memory or transmitted from the channel composite circuit, wherein the image data of the plurality of channels includes a plurality of line data, respectively, wherein the interface circuit is configured to output a first packet including a k-th line data included in an image data of the first channel, to output a second packet including a k-th line data included in an image data of the second channel after outputting the first packet, wherein the channel composite circuit is configured to transmit the k-th line data included in the image data of the first channel to the memory to store in a first address area and to transmit the k-th line data included in the image data of the second channel to the memory to store in a second address area following the first address area after the k-th line data included in the image data of the first channel is stored in the memory. ### Claim 9 (depends on 8) The image processing system according to claim 8, further comprising: an image processor configured to perform an image recognition processing for image data stored in the memory after image processing by the ISP or the image data of the plurality of channels stored in the memory by the channel composite circuit. ### Claim 10 (depends on 8) The image processing system according to claim 8, wherein the plurality of packets have a format according to MIPI (Mobile Industry Processor Interface) CSI-2 (Camera Serial Interface 2) standard. ### Claim 11 (depends on 9) The image processing system according to claim 9, wherein the channel composite circuit includes a line stride register that stores a line stride value, the line stride value is larger than a total value of line sizes in the image data of the plurality of channels and is i times of BW, where i is an integer larger or equal to than 1 and BW is bus width of the memory, and where i is the smallest, and wherein the channel composite circuit is configured to write k-th line data of image data of the plurality of channels continuously from a line start address based on LCUNT times of the line stride value, where LCUNT is an integer, and write (k+1)-th line data of image data of the plurality of channels continuously from a line address based on (LCUNT+1) times of the line stride value. ### Claim 12 (depends on 11) The image processing system according to claim 11, wherein the interface circuit outputs the plurality of packets each including line data in the image data of the plurality of channels in a predetermined channel order for each line, wherein the channel composite circuit stores a start address for each channel for the line data in a storage area that is a register or a memory, the start address is a relative address from the line start address for each line and is determined based on the predetermined channel order, and wherein the ISP or the image processor is configured to read the image data of the plurality of channels by referring the start address when the ISP or the image processor performs processing for the image data of the plurality of channels stored in the memory. ### Claim 13 (depends on 11) The image processing system according to claim 11, wherein the interface circuit outputs the plurality of packets each including line data in the image data of the plurality of channels in a variable channel order for each line, wherein the channel composite circuit stores a start address for each channel and for each line for the line data in a storage area that is a register or a memory, the start address is a relative address from the line start address for each line and is determined by recognizing the variable channel order for each line, and wherein the ISP or the image processor is configured to read the image data of the plurality of channels by referring the start address when the ISP or the image processor performs processing for the image data of the plurality of channels stored in the memory. ### Claim 14 (depends on 10) The image processing system according to claim 10, wherein the channel composite circuit includes: a packet identifying circuit provided in common to the image data of the plurality of channels and configured to identify a channel to which each of the plurality of packets belongs based on a header information of each packet, and a data extract circuit provided in common to the image data of the plurality of channels and configured to extract the line data included in each packet. ### Claim 15 (depends on 14) The image processing system according to claim 14, wherein the header information includes a virtual channel value and a data type value, and wherein the packet identifying circuit configured to identify the channel to which each of the plurality of packet belongs based on a combination of the virtual channel value and the data type value.