# US 12,603,675 B2 · Method and system for high speed cable testing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,603,675 B2 - Document ID: US12603675B2 - Status: Granted - Kind: B2 - Application number: 18/799,488 - Filed: 2024-08-09 - Published: 2025-11-13 - Granted: 2026-04-14 - Earliest claimed: 2024-05-10 - Assignees: Quanta Computer Inc. - Applicants: Quanta Computer Inc. - Inventors: Chun-Ching Yu; Chih-Chia Huang; Chih-Liang Hsu - Web page: https://patentgrep.com/patent/US12603675B2 ## CPC - H04B 3/46: Monitoring; Testing - G06F 7/582: {Pseudo-random number generators} - H04B: TRANSMISSION - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system and method for testing high speed cables for a computer system is disclosed. A test vehicle module includes a signal generator that may be a re-timer chip. The test vehicle module also includes a board management controller coupled to the signal generator. A memory is coupled to the board management controller. The memory stores diagnostic software executable by the board management controller. A connector is coupled to the signal generator to transmit and receive cable test signals from terminals of a cable through an adaptor baseboard. The controller executes the diagnostic software to send cable test signals through the signal generator, receive test signals from another test vehicle module, and generates test data from the received test signals. ## Claims ### Claim 1 A computer cable test system comprising: a first test vehicle module including a first controller and a first re-timer unit, wherein the first controller causes the first re-timer unit to generate a test signal for an end terminal of a cable; and a second test vehicle module including a second controller and a second re-timer unit, wherein the second re-timer unit receives the test signal from an opposite end terminal of the cable, and the second controller of the second test vehicle generates test data from the received test signal. ### Claim 2 (depends on 1) The system of claim 1, wherein each of the first and second controllers is a baseboard management controller (BMC), wherein the first test vehicle module includes a first memory coupled to the first controller, and wherein the second test vehicle module includes a second memory coupled to the second controller. ### Claim 3 (depends on 2) The system of claim 2, wherein each of the first and second memories is a flash memory, wherein the second controller stores the generated test data from the received test signal to a system error log in the second memory. ### Claim 4 (depends on 3) The system of claim 3, wherein the first and second controllers execute test diagnostic software to generate the test signal and the test data. ### Claim 5 (depends on 1) The system of claim 1, wherein the second controller examines the test signal for signal defects or a signal lock. ### Claim 6 (depends on 1) The system of claim 1, wherein the test signal is a pseudo random binary sequence (PRBS) checked for one of bit error rate (BER), forward error correction, or signal quality. ### Claim 7 (depends on 1) The system of claim 1, further comprising an adaptor baseboard having a first connector coupled to the first re-timer unit and a second connector coupled to a cable connector on a cartridge backplane module, wherein the cable connector holds the end terminal of the cable. ### Claim 8 (depends on 7) The system of claim 7, wherein the second connector is one of a plurality of connectors having different pin configurations, each of the plurality of connectors being attachable to a different cable connector. ### Claim 9 (depends on 7) The system of claim 7, wherein the first and second re-timer units include a plurality of re-timer chips, each of the re-timer chips having input/outputs that may be coupled to one of the terminals of the cable. ### Claim 10 (depends on 9) The system of claim 9, wherein the first controller configures a pinout for a plurality of cables including the cable in the cartridge backplane module for connection to the input/outputs of the re-timer chips. ### Claim 11 (depends on 1) The system of claim 1, wherein the second test vehicle module includes a management port allowing the test data to be accessed by an external device. ### Claim 12 A method of testing a cable, the method comprising: coupling an end terminal of the cable to a first re-timer unit on a first test vehicle module; coupling an opposite end terminal of the cable to a second re-timer unit on a second test vehicle module; transmitting a test signal from the first re-timer unit to the end terminal of the cable via a command from a first controller; receiving the test signal from the second re-timer unit from the opposite end terminal of the cable; and generating test data from the test signal via a second controller. ### Claim 13 (depends on 12) The method of claim 12, further comprising storing the test data from the received test signal in a system error log in a memory. ### Claim 14 (depends on 12) The method of claim 12, further comprising examining the test signal for signal defects or signal lock via the second controller. ### Claim 15 (depends on 12) The method of claim 12, wherein the test signal is a pseudo random binary sequence (PRBS) checked for one of bit error rate (BER), a forward error correction, or a signal quality. ### Claim 16 (depends on 12) The method of claim 12, wherein the coupling of the first re-timer unit to the end terminal of the cable includes connecting a first connector of an adaptor baseboard to the first re-timer unit and connecting a second connector of the adaptor baseboard to a cable connector on a cartridge backplane module, wherein the cable connector holds the end terminal of the cable. ### Claim 17 (depends on 16) The method of claim 16, wherein the second connector is selected from one of a plurality of connectors having different pin configurations, each of the plurality of connectors being attachable to a different cable connector. ### Claim 18 (depends on 16) The method of claim 16, wherein the first and second re-timer units include a plurality of re-timer chips, each of the re-timer chips having input/outputs couplable to one of the terminals of the cable. ### Claim 19 (depends on 18) The method of claim 18, wherein the cable is one of a plurality of cables, and the method further comprising configuring a pinout for the plurality of cables from a cable map for connection to the input/outputs of the re-timer chips. ### Claim 20 A test vehicle module comprising: a signal generator; a board management controller coupled to the signal generator; a memory coupled to the board management controller, the memory storing diagnostic software executable by the board management controller; and a connector coupled to the signal generator to transmit and receive cable test signals from terminals of a cable through an adaptor baseboard, wherein the controller executes the diagnostic software to send cable test signals through the signal generator, receive cable test signals from another test vehicle module, and generate test data from the received test signals.