US 12,603,674 B2Granted

Radio communication method and system

AssigneeSTMicroelectronics International N.V.

InventorsRiccardo Condorelli, Antonino Mondello, Michele Alessandro Carrano, Salvatore Costa, Michele Bottaro, Pascal Fabre, Philippe Bollard, Felice Alberto Torrisi

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Abstract

Method of operating a radio communication system during a stand-by time interval in a stand-by state. The method comprises: applying clock division processing to a reference clock signal and producing a divided clock signal; applying PLL processing to the divided clock signal producing a PLL clock signal; receiving at least one input signal; when the input signal has a first logic value, interrupting applying PLL processing to the divided clock signal and enabling counting clock signal edges of the divided clock signal; when said counting clock signal edges reaches a first target count value, restarting applying PLL processing; continuing counting clock signal edges until reaching a second target count value; when said counting reaches the second target count value, issuing and sampling an end-count signal based on the PLL clock signal, producing a timing clock signal as a result and providing the timing clock signal to a user circuit.

Claims20

Dependent claims

A method of operating a radio communication system during a stand-by time interval in which the radio communication system is in a stand-by state comprising:

providing a reference clock signal having a reference clock period;
applying clock division processing to the reference clock signal producing a divided clock signal as a result;
applying phase-locked loop (PLL) processing to the divided clock signal producing a PLL clock signal as a result, wherein the PLL clock signal has a PLL clock period greater than the reference clock period;
receiving at least one input signal during a first part of the stand-by time interval;
in response to the at least one input signal having a first logic value, interrupting the applying PLL processing to the divided clock signal and enabling counting clock signal edges of the divided clock signal;
in response to the counting clock signal edges of the divided clock signal reaching a first target count value, and during a second part of the stand-by time interval, restarting the applying PLL processing to the divided clock signal;
continuing the counting clock signal edges of the divided clock signal until reaching a second target count value;
in response to the counting clock signal edges of the divided clock signal reaching the second target count value, and during a third part of the stand-by time interval, issuing an end-count signal and sampling the end-count signal based on the PLL clock signal producing a timing clock signal as a result;
and
providing the timing clock signal to a user circuit.

7 more elements

A radio communication system configured to be operated during a stand-by time interval in which the radio communication system is in a stand-by state, the radio communication system comprising:

a reference clock generator circuit block configured to provide a reference clock signal having a reference clock period;
a clock division processing circuit block configured to apply clock division processing to the reference clock signal, producing a divided clock signal as a result;
a phase-locked loop (PLL) circuit block configured to apply PLL processing to the divided clock signal, producing a PLL clock signal as a result, the PLL clock signal having a PLL clock period greater than the reference clock period;
a first input node configured to receive at least one input signal, during a first part of a stand-by time interval;
processing circuitry comprising a counter circuit, the processing circuitry configured to:
in response to the at least one input signal having a first logic value, asserting an interrupt signal and providing the interrupt signal to the PLL circuit block, thereby interrupting the applying PLL processing to the divided clock signal and enabling the counter circuit to count clock signal edges of the divided clock signal;
in response to the counter circuit reaching a first target count value, during a second part of the stand-by time interval, restart the applying PLL processing to the divided clock signal;
continue the counting, via the counter circuit, of the clock signal edges of the divided clock signal until reaching a second target count value,
in response to the counter circuit reaching the second target count value, during a third part of the stand-by time interval, issuing an end-count signal and sampling the end-count signal based on the PLL clock signal, producing a timing clock signal as a result, and
timing circuitry configured to provide the timing clock signal to a user circuit.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/651,120Filed 30 Apr 2024
Priority: IT 10202300001111231 May 2023
Published: US 2024/0405798 A15 Dec 2024
Granted: 14 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03L 7/0802
Details of the phase-locked loop: the loop being adapted for reducing power consumption
H04B 1/7183
Using impulse radio: synchronisation
H03L 7/18
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop:…
H04B 1/40
Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of…: circuits