# US 12,603,669 B2 · Calibration techniques for alternating-current (AC)-coupled transceiver

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- Number: US 12,603,669 B2
- Document ID: US12603669B2
- Status: Granted
- Kind: B2
- Application number: 18/765,602
- Filed: 2024-07-08
- Published: 2026-01-08
- Granted: 2026-04-14
- Earliest claimed: 2024-07-08
- Assignees: NVIDIA Corporation
- Applicants: NVIDIA Corporation
- Inventors: Chun-Ju Shen; Ying Wei; Vishnu Balan; Haiming Tang
- Web page: https://patentgrep.com/patent/US12603669B2

## CPC

- H04B 1/16: Circuits
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H04B: TRANSMISSION
- H03F: AMPLIFIERS

## Abstract

A circuit includes a receiver coupled to an input node and includes a transimpedance amplifier (TIA). The input node is to be coupled to a transmitter over a channel. Calibration circuitry is coupled to the input node and to modify a resistance of a feedback resistor of the receiver by applying a plurality of control values. The calibration circuitry is to generate, for each applied control value, a first digital code for a direct current (DC) swing and a second digital code for an alternating current (AC) swing at the input node. The calibration circuitry is to determine a final control value of the plurality of control values that minimizes a difference between the first and second digital codes.

## Claims

### Claim 1

A circuit comprising:
a receiver coupled to an input node and comprising a transimpedance amplifier, wherein the input node is to be coupled to a transmitter over a channel; and
calibration circuitry coupled to the input node, the calibration circuitry to:
modify a resistance of a feedback resistor of the receiver by applying a plurality of control values;
generate, for each applied control value, a first digital code for a direct current (DC) swing and a second digital code for an alternating current (AC) swing at the input node; and
determine a final control value of the plurality of control values that minimizes a difference between the first and second digital codes.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the feedback resistor is one of a negative feedback resistor or a positive feedback resistor, and wherein the transimpedance amplifier comprises the negative feedback resistor, further comprising an inverter coupled to the transimpedance amplifier, and wherein the positive feedback resistor is coupled across the transimpedance amplifier and the inverter.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the receiver further comprises a deserializer coupled to an output of the inverter and to sample, using a local asynchronous clock, an output signal of the inverter to determine a number of one values and zero values, wherein the calibration circuitry is further to:
retrieve, from the deserializer, the number of one values and zero values;
determine a duty cycle based on the number of one values compared to the number of zero values; and
inject, at the input node, a DC offset voltage to shift an input common mode voltage to bring the duty cycle towards 50%.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein the calibration circuitry further comprises:
a low-pass filter (LPF) coupled to the inverter to extract an output common mode voltage of the transimpedance amplifier; and
a comparator coupled to the LPF, the comparator to compare the output common mode voltage to a reference voltage; and
wherein the calibration circuitry is further to adjust relative strengths of p-type metal-oxide semiconductor (PMOS) and N-type metal-oxide semiconductor (NMOS) transistors of the transimpedance amplifier and the inverter to skew rising or falling edges of the output common mode voltage towards those of the reference voltage.

### Claim 5 (depends on 3)

The circuit of claim 3, wherein the feedback resistor is one of a negative feedback resistor or a positive feedback resistor that is programmable by the plurality of control values, and wherein the calibration circuitry is further to set the resistance of the one of the negative feedback resistor or the positive feedback resistor using the final control value and is to be disabled after calibration.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein the feedback resistor is one of a negative feedback resistor or a positive feedback resistor, and wherein the calibration circuitry comprises:
a peak detector coupled to the input node, the peak detector to variably detect, at different times, a DC voltage and an envelope of an AC voltage;
an analog-to-digital converter (ADC) coupled to the peak detector, the ADC to generate the first digital code based on the detected DC voltage and the second digital code based on the detected envelope of the AC voltage; and
a calibration engine coupled between the ADC and the one of the negative feedback resistor or the positive feedback resistor, wherein the calibration engine is to:
incrementally modify the resistance using each control value of the plurality of control values;
determine each difference between the first and second digital codes while applying a respective control value of the plurality of control values; and
identify the final control value based on the differences between the first and second digital codes for the plurality of control values.

### Claim 7 (depends on 6)

The circuit of claim 6, wherein the calibration engine is further to:
determine that the transmitter is inactive and an input of the receiver is reset before reading each first digital code from the ADC; and
determine that the transmitter is toggling according to a clock pattern before reading each second digital code from the ADC.

### Claim 8 (depends on 6)

The circuit of claim 6, wherein the detected DC voltage is a minimum DC voltage formed by the positive and negative feedback resistors and a detected low-sided envelope of the AC voltage is a minimum AC voltage, and wherein the peak detector comprises:
a plurality of p-type metal-oxide semiconductor (PMOS) transistors that are source-drain coupled and that have gates coupled together; and
a capacitor coupled to an output of a first PMOS transistor, of the plurality of PMOS transistors, that is coupled to ground, wherein a current of the peak detector is asymmetrically modulated by an input voltage to the plurality of PMOS transistors so that the peak detector functions as a single-direction rectifier biased towards the minimum DC voltage.

### Claim 9 (depends on 6)

The circuit of claim 6, wherein the detected DC voltage is a maximum DC voltage formed by the positive and negative feedback resistors and a detected high-sided envelope of the AC voltage is a maximum AC voltage, and wherein the peak detector comprises:
a plurality of n-type metal-oxide semiconductor (NMOS) transistors that are source-drain coupled and that have gates coupled together; and
a capacitor coupled to an output of a first NMOS transistor, of the plurality of NMOS transistors, that is coupled to a supply voltage, wherein a current of the peak detector is asymmetrically modulated by an input voltage to the plurality of NMOS transistors so that the peak detector functions as a single-direction rectifier biased towards the maximum DC voltage.

### Claim 10

A system comprising:
a first device comprising a capacitor coupled to a first side of a channel and a transmitter coupled to the capacitor;
a second device comprising a receiver having a transimpedance amplifier coupled to an input node, wherein the input node is to be coupled to a second side of the channel; and
calibration circuitry coupled between the input node and the capacitor, the calibration circuitry to:
modify a capacitance of the capacitor based on each of a plurality of control values;
generate, for each control value, a first digital code for a direct current (DC) swing and a second digital code for an alternating current (AC) swing at the input node; and
determine a final control value of the plurality of control values that minimizes a difference between the first and second digital codes.

### Claim 11 (depends on 10)

The system of claim 10, wherein the capacitor is programmable by the plurality of control values, further comprising a back channel coupled between the calibration circuitry and the capacitor.

### Claim 12 (depends on 10)

The system of claim 10, wherein the calibration circuitry is further to set the capacitance of the capacitor using the final control value and is to be disabled after calibration.

### Claim 13 (depends on 10)

The system of claim 10, wherein the calibration circuitry comprises:
a peak detector coupled to the input node, the peak detector to variably detect, at different times, a DC voltage and an envelope of an AC voltage;
an analog-to-digital converter (ADC) coupled to the peak detector, the ADC to generate the first digital code based on the detected DC voltage and the second digital code based on the detected envelope of the AC voltage; and
a calibration engine coupled between the ADC and the capacitor, wherein the calibration engine is to:
incrementally modify the capacitance using each control value of the plurality of control values;
determine each difference between the first and second digital codes while applying a respective control value of the plurality of control values; and
identify the final control value based on the differences between the first and second digital codes for the plurality of control values.

### Claim 14 (depends on 13)

The system of claim 13, wherein the calibration engine is further to:
determine that the transmitter is inactive and an input of the receiver is reset before reading each first digital code from the ADC; and
determine that the transmitter is toggling according to a clock pattern before reading each second digital code from the ADC.

### Claim 15 (depends on 13)

The system of claim 13, wherein the detected DC voltage is a minimum DC voltage formed by positive and negative feedback resistors of the receiver and a detected low-sided envelope of the AC voltage is a minimum AC voltage, and wherein the peak detector comprises:
a plurality of p-type metal-oxide semiconductor (PMOS) transistors that are source-drain coupled and that have gates coupled together; and
a capacitor coupled to an output of a first PMOS transistor, of the plurality of PMOS transistors, that is coupled to ground, wherein a current of the peak detector is asymmetrically modulated by an input voltage to the plurality of PMOS transistors so that the peak detector functions as a single-direction rectifier biased towards the minimum DC voltage.

### Claim 16 (depends on 13)

The system of claim 13, wherein the detected DC voltage is a maximum DC voltage formed by positive and negative feedback resistors of the receiver and a detected high-sided envelope of the AC voltage is a maximum AC voltage, and wherein the peak detector comprises:
a plurality of n-type metal-oxide semiconductor (NMOS) transistors that are source-drain coupled and that have gates coupled together; and
a capacitor coupled to an output of a first NMOS transistor, of the plurality of NMOS transistors, that is coupled to a supply voltage, wherein a current of the peak detector is asymmetrically modulated by an input voltage to the plurality of NMOS transistors so that the peak detector functions as a single-direction rectifier biased towards the maximum DC voltage.

### Claim 17 (depends on 10)

The system of claim 10, further comprising:
an inverter coupled to the transimpedance amplifier;
a positive feedback resistor coupled across the transimpedance amplifier and the inverter; and
a deserializer coupled to an output of the inverter and to sample, using a local asynchronous clock, an output signal of the inverter to determine a number of one values and zero values;
wherein the calibration circuitry is further to:
retrieve, from the deserializer, the number of one values and zero values;
determine a duty cycle based on the number of one values compared to the number of zero values; and
inject, at the input node, a DC offset voltage to shift an input common mode voltage to bring the duty cycle towards 50%.

### Claim 18 (depends on 10)

The system of claim 10, wherein the transimpedance amplifier has a negative feedback resistor coupled to the input node, further comprising:
an inverter coupled to the transimpedance amplifier; and
a positive feedback resistor coupled across the transimpedance amplifier and the inverter;
wherein the calibration circuitry further comprises:
a low-pass filter (LPF) coupled to the inverter to extract an output common mode voltage of the transimpedance amplifier; and
a comparator coupled to the LPF, the comparator to compare the output common mode voltage to a reference voltage; and
wherein the calibration circuitry is further to adjust relative strengths of p-type metal-oxide semiconductor (PMOS) and n-type metal-oxide semiconductor (NMOS) transistors of the transimpedance amplifier and the inverter to skew rising or falling edges of the output common mode voltage towards rising or falling edges of the reference voltage.

### Claim 19

A circuit comprising:
a receiver to be coupled to a channel, which is coupled to a transmitter, wherein the receiver comprises:
at least one capacitor coupled between the channel and a ground; and
a transimpedance amplifier coupled to an input node coupled to the channel; and
calibration circuitry coupled between the input node and the at least one capacitor, the calibration circuitry to:
modify a capacitance of the at least one capacitor based on each of a plurality of control values;
generate, for each control value, a first digital code for a direct current (DC) swing and a second digital code for an alternating current (AC) swing at the input node; and
determine a final control value of the plurality of control values that minimizes a difference between the first and second digital codes.

### Claim 20 (depends on 19)

The circuit of claim 19, wherein the at least one capacitor is programmable by the plurality of control values, and wherein the receiver further comprises:
an inverter coupled to the transimpedance amplifier; and
a positive feedback resistor coupled across the transimpedance amplifier and the inverter.

### Claim 21 (depends on 19)

The circuit of claim 19, wherein the calibration circuitry is further to set the capacitance of the at least one capacitor using the final control value and is to be disabled after calibration.

### Claim 22 (depends on 19)

The circuit of claim 19, wherein the calibration circuitry comprises:
a peak detector coupled to the input node, the peak detector to variably detect, at different times, a DC voltage and an envelope of an AC voltage;
an analog-to-digital converter (ADC) coupled to the peak detector, the ADC to generate the first digital code based on the detected DC voltage and the second digital code based on the detected envelope of the AC voltage; and
a calibration engine coupled between the ADC and the at least one capacitor, wherein the calibration engine is to:
incrementally modify the capacitance using each control value of the plurality of control values;
determine each difference between the first and second digital codes while using a respective control value of the plurality of control values; and
identify the final control value based on the differences between the first and second digital codes for the plurality of control values.

### Claim 23 (depends on 22)

The circuit of claim 22, wherein the calibration engine is further to:
determine that the transmitter is inactive and an input of the receiver is reset before reading each first digital code from the ADC; and
determine that the transmitter is toggling according to a clock pattern before reading each second digital code from the ADC.

### Claim 24 (depends on 22)

The circuit of claim 22, wherein the detected DC voltage is a minimum DC voltage formed by positive and negative feedback resistors of the receiver and a detected low-sided envelope of the AC voltage is a minimum AC voltage, and wherein the peak detector comprises:
a plurality of p-type metal-oxide semiconductor (PMOS) transistors that are source-drain coupled and that have gates coupled together; and
a capacitor coupled to an output of a first PMOS transistor, of the plurality of PMOS transistors, that is coupled to ground, wherein a current of the peak detector is asymmetrically modulated by an input voltage to the plurality of PMOS transistors so that the peak detector functions as a single-direction rectifier biased towards the minimum DC voltage.

### Claim 25 (depends on 22)

The circuit of claim 22, wherein the detected DC voltage is a maximum DC voltage formed by positive and negative feedback resistors of the receiver and a detected high-sided envelope of the AC voltage is a maximum AC voltage, and wherein the peak detector comprises:
a plurality of n-type metal-oxide semiconductor (NMOS) transistors that are source-drain coupled and that have gates coupled together; and
a capacitor coupled to an output of a first NMOS transistor, of the plurality of NMOS transistors, that is coupled to a supply voltage, wherein a current of the peak detector is modulated by an input voltage to the plurality of NMOS transistors so that the peak detector functions as a single-direction rectifier biased towards the maximum DC voltage.

### Claim 26 (depends on 19)

The circuit of claim 19, further comprising:
an inverter coupled to the transimpedance amplifier;
a positive feedback resistor coupled across the transimpedance amplifier and the inverter; and
a deserializer coupled to an output of the inverter and to sample, using a local asynchronous clock, an output signal of the inverter to determine a number of one values and zero values;
wherein the calibration circuitry is further to:
retrieve, from the deserializer, the number of one values and zero values;
determine a duty cycle based on the number of one values compared to the number of zero values; and
inject, at the input node, a DC offset voltage to shift an input common mode voltage to bring the duty cycle towards 50%.

### Claim 27 (depends on 19)

The circuit of claim 19, wherein the transimpedance amplifier has a negative feedback resistor coupled to the input node, further comprising:
an inverter coupled to the transimpedance amplifier;
a positive feedback resistor coupled across the transimpedance amplifier and the inverter;
wherein the calibration circuitry further comprises:
a low-pass filter (LPF) coupled to the inverter to extract an output common mode voltage of the transimpedance amplifier; and
a comparator coupled to the LPF, the comparator to compare the output common mode voltage to a reference voltage; and
wherein the calibration circuitry is further to adjust relative strengths of PMOS and NMOS transistors of the transimpedance amplifier and the inverter to skew rising or falling edges of the output common mode voltage towards those of the reference voltage.