Encoder
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWin-San Khwa, Hiroki Noguchi, Ku-Feng Lin
Life of this patent
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Abstract
An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.
Claims20
An apparatus comprising:
- a first stage comprising a 7:1 decoder configured to:
- receive a first input comprising an input code,
- decode the first input, and
- produce a first output comprising the decoded first input on seven output nodes of the 7:1 decoder;
- and
- a second stage configured to;
- receive the first output from the first stage,
- receive a second input,
- convert the first output and the second input from a first code to a second code based on the second input and the first output.
An apparatus comprising:
- a first stage comprising a 7:1 decoder configured to:
- receive a first input comprising a 0th bit, a 1st bit, and a 2nd bit of an input code,
- decode the first input, and
- produce a first output comprising the decoded first input on seven output nodes of the 7:1 decoder;
- and
- a second stage comprising a first plurality of two input port AND gates, each one of the first plurality of two input port AND gates having a first input port respectively connected to one of seven output nodes of the 7:1 decoder and a second input port connected to an inverse of a 3rd bit of the input code.
An apparatus comprising:
- a first stage comprising a 7:1 decoder, wherein the 7:1 decoder decodes a first input to produce a first output on seven output nodes of the 7:1 decoder;
- and
- a second stage connected to the first stage, wherein the second stage is configured to convert the first output and a second input from a first code to a second code based on the second input and the first output, and wherein the second stage comprises a first plurality of two input port AND gates, each one of the first plurality of two input port AND gates having a first input port respectively connected to one of seven output nodes of the 7:1 decoder and a second input port connected to an inverse of a 3rd bit of the input code.
Dependencies are inferred from the claim text.